[PATCH] D87543: AMDGPU: Always split si_end_cf blocks

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D87543#2303595 <https://reviews.llvm.org/D87543#2303595>, @arsenm wrote:

> In D87543#2303584 <https://reviews.llvm.org/D87543#2303584>, @nhaehnle wrote:
>
>> It's unclear to me what this is trying to achieve. If it is to prevent
>>
>>   bb:
>>     <-- reload inserted here during live range splitting
>>     $exec = S_OR_B64 $exec, %other
>>     ... rest of code ...
>>
>> ... then this change only replaces it by:
>>
>>   bb:
>>     <-- reload inserted here during live range splitting
>>     $exec = S_OR_B64_term $exec, %other
>>     // fallthrough
>>   
>>   bb.new:
>>     ... rest of code ...
>>
>> The inserted reload code is as incorrect as it was before.
>
> I'm not trying to fully solve the live range splitting problem greedy regalloc hits. I'm trying to eliminate the isBasicBlockPrologue concept that fastregalloc trips over when inserting spills at the beginning of the block

I still not not see how you can get away without isBasicBlockPrologue. I can see how splitting can help with it, but not without. You can split everything and have S_OR the only instruction, but that does not prevent RA from inserting a reload right before it into the same BB.


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  https://reviews.llvm.org/D87543/new/

https://reviews.llvm.org/D87543