[PATCH] D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.

LGTM as well.



================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1451
+
+  def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 PPR:$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))),
+            (FCVT_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>;
----------------
paulwalker-arm wrote:
> sdesmalen wrote:
> > This matches both 0 and 1, but is otherwise ignored in this pattern.
> > I wonder if this should match only `0` for normal rounding?
> I don't believe the "extra" operand affects the functional requirements of the node, so it's not the case that you need to select "normal rounding" or something else. It looks to be purely an optimisation aid and I don't know why it's not a flag like isExact(), which can be attached to things like shifts.
Okay, I guess that's fine then. I see the `fpround` SDNode also doesn't reflect that operand.

```def SDTFPRoundOp  : SDTypeProfile<1, 1, [   // fround
  SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>
]>;
def fpround    : SDNode<"ISD::FP_ROUND"   , SDTFPRoundOp>;```

nit: @kmclaughlin could you maybe just add a comment that the operand for the 'precise' flag, matched by `(i64 timm0_1)`, is ignored?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88321/new/

https://reviews.llvm.org/D88321