[PATCH] D88444: [SVE] Lower fixed length VECREDUCE_[FMAX|FMIN] to Scalable

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9671-9673
+  bool OverrideNEON = Op.getOpcode() != ISD::VECREDUCE_ADD &&
+                      (SrcVT.getVectorElementType() == MVT::i64 ||
+                       SrcVT.getVectorElementType() == MVT::f16);
----------------
There are f16 MAX/MIN reduction instructions for NEON, it's just they're an optional v8.2 extension.  However, when SVE is implemented the extension is mandatory so we can rely on them.

I did a quick test using your tests against master and they just worked.


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:198
+; VBITS_GE_1048-NEXT: fmaxnmv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_1048-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_1048-NEXT: ret
----------------
What's going on here?


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll:210
+; VBITS_GE_2096-NEXT: fmaxnmv [[REDUCE:d[0-9]+]], [[PG]], [[OP]].d
+; VBITS_GE_2096-NEXT: fmov x0, [[REDUCE]]
+; VBITS_GE_2096-NEXT: ret
----------------
And here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88444/new/

https://reviews.llvm.org/D88444