[PATCH] D88201: [DAGCombiner] Add decomposition patterns for Mul-by-Imm.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:3647
+    unsigned TZeros = MulC == 2 ? 0 : MulC.countTrailingZeros();
+    MulC = MulC.lshr(TZeros);
     if ((MulC - 1).isPowerOf2())
----------------
MulC.lshrInPlace(TZeros);


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15944
+    if (ConstNode->getAPIntValue().getBitWidth() > 8 * sizeof(int64_t))
+      return false;
+    // This transformation will generate >= 2 operations. But the following
----------------
Maybe better to use ConstNode->getAPIntValue().isSignedIntN() ?


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  https://reviews.llvm.org/D88201/new/

https://reviews.llvm.org/D88201