[llvm] 6c81683 - Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar."

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2020-09-28T11:25:19-07:00
New Revision: 6c8168324b5329c94fe7e8f9a1619802091b9bec

URL: https://github.com/llvm/llvm-project/commit/6c8168324b5329c94fe7e8f9a1619802091b9bec
DIFF: https://github.com/llvm/llvm-project/commit/6c8168324b5329c94fe7e8f9a1619802091b9bec.diff

LOG: Revert "[AArch64][GlobalISel] Add selection support for <8 x s16>  G_INSERT_VECTOR_ELT with GPR scalar."

This reverts commit b5e87c9ef2243ecd65e0ef87a1bf303c0c26db04 as it seems to have
broken a bot.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 53875db57c0d..78f379b347ab 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3806,10 +3806,7 @@ static std::pair<unsigned, unsigned>
 getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
   unsigned Opc, SubregIdx;
   if (RB.getID() == AArch64::GPRRegBankID) {
-    if (EltSize == 16) {
-      Opc = AArch64::INSvi16gpr;
-      SubregIdx = AArch64::ssub;
-    } else if (EltSize == 32) {
+    if (EltSize == 32) {
       Opc = AArch64::INSvi32gpr;
       SubregIdx = AArch64::ssub;
     } else if (EltSize == 64) {

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
index a311e005a574..5c4a2e1c3544 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
@@ -1,32 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
 ---
-name:            v8s16_gpr
-alignment:       4
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-body:             |
-  bb.0:
-    liveins: $q1, $w0
-
-    ; CHECK-LABEL: name: v8s16_gpr
-    ; CHECK: liveins: $q1, $w0
-    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
-    ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
-    ; CHECK: $q0 = COPY [[INSvi16gpr]]
-    ; CHECK: RET_ReallyLR implicit $q0
-    %0:gpr(s32) = COPY $w0
-    %trunc:gpr(s16) = G_TRUNC %0
-    %1:fpr(<8 x s16>) = COPY $q1
-    %3:gpr(s32) = G_CONSTANT i32 1
-    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32)
-    $q0 = COPY %2(<8 x s16>)
-    RET_ReallyLR implicit $q0
-
-...
----
 name:            v8s16_fpr
 alignment:       4
 legalized:       true