[PATCH] D87046: [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

Xiangling Liao via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 25 10:51:50 PDT 2020


Xiangling_L added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:21
+; 32BIT-DAG:     slwi [[REG4:[0-9]+]], [[REG2]], 8
+; 32BIT-DAG:     rlwimi [[REG3]], [[REG1]], 8, 0, 23
+; 32BIT-DAG:     stw [[REG4]], 4(4)
----------------
It seems, [[REG3]] does not need to be the same register as the one used in `rotlwi`?



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Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:22
+; 32BIT-DAG:     rlwimi [[REG3]], [[REG1]], 8, 0, 23
+; 32BIT-DAG:     stw [[REG4]], 4(4)
+; 32BIT-DAG:     stw [[REG3]], 0(4)
----------------
I am wondering why we don't use regex to match register 4 here?


================
Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:27
+; 64BIT:         extswsli [[REG1:[0-9]+]], {{[0-9]+}}, 8
+; 64BIT-NEXT:    std [[REG1]], 0(4)
+; 64BIT-NEXT:    blr
----------------
Same question as above.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87046/new/

https://reviews.llvm.org/D87046



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