[PATCH] D88321: [SVE][CodeGen] Lower scalable fp_extend & fp_round operations

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15926
   for (const SDValue &V : Op->op_values()) {
-    assert((isa<CondCodeSDNode>(V) || V.getValueType().isScalableVector()) &&
+    assert((!V.getValueType().isVector() ||
+            V.getValueType().isScalableVector()) &&
----------------
is this change intentional?


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1451
+
+  def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 PPR:$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))),
+            (FCVT_ZPmZ_StoH ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>;
----------------
This matches both 0 and 1, but is otherwise ignored in this pattern.
I wonder if this should match only `0` for normal rounding?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88321/new/

https://reviews.llvm.org/D88321