[llvm] a3d0dce - [ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
Meera Nakrani via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 22 04:54:39 PDT 2020
Author: Meera Nakrani
Date: 2020-09-22T11:54:10Z
New Revision: a3d0dce2608bb399f2bf0122d8c6a4c7b4d6c1fa
URL: https://github.com/llvm/llvm-project/commit/a3d0dce2608bb399f2bf0122d8c6a4c7b4d6c1fa
DIFF: https://github.com/llvm/llvm-project/commit/a3d0dce2608bb399f2bf0122d8c6a4c7b4d6c1fa.diff
LOG: [ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
Changes TTI function getIntImmCostInst to take an additional Instruction parameter,
which enables us to be able to check it is part of a min(max())/max(min()) pattern that will match SSAT.
We can then mark the constant used as free to prevent it being hoisted so SSAT can still be generated.
Required minor changes in some non-ARM backends to allow for the optional parameter to be included.
Differential Revision: https://reviews.llvm.org/D87457
Added:
Modified:
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.h
llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 9bf821fa1e3b..297cc8e55fb4 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -810,8 +810,9 @@ class TargetTransformInfo {
/// Return the expected cost of materialization for the given integer
/// immediate of the specified type for a given instruction. The cost can be
/// zero if the immediate can be folded into the specified instruction.
- int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm,
- Type *Ty, TargetCostKind CostKind) const;
+ int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty,
+ TargetCostKind CostKind,
+ Instruction *Inst = nullptr) const;
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TargetCostKind CostKind) const;
@@ -1461,7 +1462,8 @@ class TargetTransformInfo::Concept {
virtual int getIntImmCost(const APInt &Imm, Type *Ty,
TargetCostKind CostKind) = 0;
virtual int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm,
- Type *Ty, TargetCostKind CostKind) = 0;
+ Type *Ty, TargetCostKind CostKind,
+ Instruction *Inst = nullptr) = 0;
virtual int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
const APInt &Imm, Type *Ty,
TargetCostKind CostKind) = 0;
@@ -1850,9 +1852,10 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
TargetCostKind CostKind) override {
return Impl.getIntImmCost(Imm, Ty, CostKind);
}
- int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm,
- Type *Ty, TargetCostKind CostKind) override {
- return Impl.getIntImmCostInst(Opc, Idx, Imm, Ty, CostKind);
+ int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty,
+ TargetCostKind CostKind,
+ Instruction *Inst = nullptr) override {
+ return Impl.getIntImmCostInst(Opc, Idx, Imm, Ty, CostKind, Inst);
}
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TargetCostKind CostKind) override {
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 7f4207411966..ebd1beb6e39e 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -314,7 +314,8 @@ class TargetTransformInfoImplBase {
}
unsigned getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind) {
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr) {
return TTI::TCC_Free;
}
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 2ffe4ff5a823..efecb4501853 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -570,11 +570,11 @@ int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty,
return Cost;
}
-int
-TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
- const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind) const {
- int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind);
+int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
+ const APInt &Imm, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) const {
+ int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
assert(Cost >= 0 && "TTI should not produce negative costs!");
return Cost;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fb23bc641573..3ec7411b1bad 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -84,7 +84,8 @@ int AArch64TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
int AArch64TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind) {
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 3c3a246b90a1..be27849bc19f 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -74,7 +74,8 @@ class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
int getIntImmCost(int64_t Val);
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind);
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TTI::TargetCostKind CostKind);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index ce3910754e5b..aad8f0344e40 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -284,8 +284,43 @@ int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
return 1;
}
-int ARMTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind) {
+// Checks whether Inst is part of a min(max()) or max(min()) pattern
+// that will match to an SSAT instruction
+static bool isSSATMinMaxPattern(Instruction *Inst, const APInt &Imm) {
+ Value *LHS, *RHS;
+ ConstantInt *C;
+ SelectPatternFlavor InstSPF = matchSelectPattern(Inst, LHS, RHS).Flavor;
+
+ if (InstSPF == SPF_SMAX &&
+ PatternMatch::match(RHS, PatternMatch::m_ConstantInt(C)) &&
+ C->getValue() == Imm && Imm.isNegative() && (-Imm).isPowerOf2()) {
+
+ auto isSSatMin = [&](Value *MinInst) {
+ if (isa<SelectInst>(MinInst)) {
+ Value *MinLHS, *MinRHS;
+ ConstantInt *MinC;
+ SelectPatternFlavor MinSPF =
+ matchSelectPattern(MinInst, MinLHS, MinRHS).Flavor;
+ if (MinSPF == SPF_SMIN &&
+ PatternMatch::match(MinRHS, PatternMatch::m_ConstantInt(MinC)) &&
+ MinC->getValue() == ((-Imm) - 1))
+ return true;
+ }
+ return false;
+ };
+
+ if (isSSatMin(Inst->getOperand(1)) ||
+ (Inst->hasNUses(2) && (isSSatMin(*Inst->user_begin()) ||
+ isSSatMin(*(++Inst->user_begin())))))
+ return true;
+ }
+ return false;
+}
+
+int ARMTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
+ const APInt &Imm, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
// Division by a constant can be turned into multiplication, but only if we
// know it's constant. So it's not so much that the immediate is cheap (it's
// not), but that the alternative is worse.
@@ -324,6 +359,12 @@ int ARMTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Im
if (Opcode == Instruction::Xor && Imm.isAllOnesValue())
return 0;
+ // Ensures negative constant of min(max()) or max(min()) patterns that
+ // match to SSAT instructions don't get hoisted
+ if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) &&
+ Ty->getIntegerBitWidth() <= 32 && isSSATMinMaxPattern(Inst, Imm))
+ return 0;
+
return getIntImmCost(Imm, Ty, CostKind);
}
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 3ffe31ba883c..4189eba111e3 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -126,7 +126,8 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind);
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
/// @}
diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
index 7366d5059c9f..263f838e44a6 100644
--- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
@@ -67,7 +67,8 @@ class LanaiTTIImpl : public BasicTTIImplBase<LanaiTTIImpl> {
}
int getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind) {
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr) {
return getIntImmCost(Imm, Ty, CostKind);
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index 5db5ab47f29e..afe963234174 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -234,9 +234,10 @@ int PPCTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
int PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind) {
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
if (DisablePPCConstHoist)
- return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind);
+ return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
assert(Ty->isIntegerTy());
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index d9aab298c7c1..a6dc96d42012 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -52,7 +52,8 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
TTI::TargetCostKind CostKind);
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind);
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TTI::TargetCostKind CostKind);
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index bd78f801c59a..44b223a4b840 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -30,8 +30,10 @@ int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
getST()->is64Bit());
}
-int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind) {
+int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
+ const APInt &Imm, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
assert(Ty->isIntegerTy() &&
"getIntImmCost can only estimate cost of materialising integers");
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 392700707760..8d077e946305 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -42,8 +42,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
TLI(ST->getTargetLowering()) {}
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
- int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind);
+ int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TTI::TargetCostKind CostKind);
};
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index 8758ddee0aab..23b061f6d862 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -64,8 +64,9 @@ int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
}
int SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
- const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind) {
+ const APInt &Imm, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
index 1aa31ff1690c..8b3b51323d93 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
@@ -41,7 +41,8 @@ class SystemZTTIImpl : public BasicTTIImplBase<SystemZTTIImpl> {
int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind);
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TTI::TargetCostKind CostKind);
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 8ce9749dc2d6..2a9bdde66bd8 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -3841,8 +3841,10 @@ int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
return std::max(1, Cost);
}
-int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
- Type *Ty, TTI::TargetCostKind CostKind) {
+int X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
+ const APInt &Imm, Type *Ty,
+ TTI::TargetCostKind CostKind,
+ Instruction *Inst) {
assert(Ty->isIntegerTy());
unsigned BitSize = Ty->getPrimitiveSizeInBits();
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h
index 8d2fa27ee7b0..687870b6f30e 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.h
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h
@@ -203,8 +203,9 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind);
- int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
- TTI::TargetCostKind CostKind);
+ int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
+ Type *Ty, TTI::TargetCostKind CostKind,
+ Instruction *Inst = nullptr);
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty, TTI::TargetCostKind CostKind);
bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
diff --git a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
index 7c14b69d658d..b3dfb7fe2463 100644
--- a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
+++ b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp
@@ -366,9 +366,9 @@ void ConstantHoistingPass::collectConstantCandidates(
ConstInt->getValue(), ConstInt->getType(),
TargetTransformInfo::TCK_SizeAndLatency);
else
- Cost = TTI->getIntImmCostInst(Inst->getOpcode(), Idx, ConstInt->getValue(),
- ConstInt->getType(),
- TargetTransformInfo::TCK_SizeAndLatency);
+ Cost = TTI->getIntImmCostInst(
+ Inst->getOpcode(), Idx, ConstInt->getValue(), ConstInt->getType(),
+ TargetTransformInfo::TCK_SizeAndLatency, Inst);
// Ignore cheap integer constants.
if (Cost > TargetTransformInfo::TCC_Basic) {
@@ -418,8 +418,9 @@ void ConstantHoistingPass::collectConstantCandidates(
// usually lowered to a load from constant pool. Such operation is unlikely
// to be cheaper than compute it by <Base + Offset>, which can be lowered to
// an ADD instruction or folded into Load/Store instruction.
- int Cost = TTI->getIntImmCostInst(Instruction::Add, 1, Offset, PtrIntTy,
- TargetTransformInfo::TCK_SizeAndLatency);
+ int Cost =
+ TTI->getIntImmCostInst(Instruction::Add, 1, Offset, PtrIntTy,
+ TargetTransformInfo::TCK_SizeAndLatency, Inst);
ConstCandVecType &ExprCandVec = ConstGEPCandMap[BaseGV];
ConstCandMapType::iterator Itr;
bool Inserted;
diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
index 36e620d50758..9b88f57126fb 100644
--- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
@@ -1106,8 +1106,7 @@ define arm_aapcs_vfpcc void @ssatmul_4_q15(i16* nocapture readonly %pSrcA, i16*
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: beq .LBB5_8
+; CHECK-NEXT: cbz r3, .LBB5_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #3
; CHECK-NEXT: bhi .LBB5_3
@@ -1139,23 +1138,16 @@ define arm_aapcs_vfpcc void @ssatmul_4_q15(i16* nocapture readonly %pSrcA, i16*
; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21
-; CHECK-NEXT: movw r0, #32768
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: movt r0, #65535
-; CHECK-NEXT: movw r1, #32767
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB5_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsh r2, [r12], #2
-; CHECK-NEXT: ldrsh r3, [r6], #2
-; CHECK-NEXT: muls r2, r3, r2
-; CHECK-NEXT: mov r3, r0
-; CHECK-NEXT: cmp.w r0, r2, asr #15
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r3, r2, #15
-; CHECK-NEXT: cmp r3, r1
-; CHECK-NEXT: csel r2, r3, r1, lt
-; CHECK-NEXT: strh r2, [r4], #2
+; CHECK-NEXT: ldrsh r0, [r12], #2
+; CHECK-NEXT: ldrsh r1, [r6], #2
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #15
+; CHECK-NEXT: ssat r0, #16, r0
+; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB5_7
; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
@@ -1280,23 +1272,16 @@ define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16*
; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21
-; CHECK-NEXT: movw r0, #32768
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: movt r0, #65535
-; CHECK-NEXT: movw r1, #32767
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB6_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsh r2, [r12], #2
-; CHECK-NEXT: ldrsh r3, [r6], #2
-; CHECK-NEXT: muls r2, r3, r2
-; CHECK-NEXT: mov r3, r0
-; CHECK-NEXT: cmp.w r0, r2, asr #15
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r3, r2, #15
-; CHECK-NEXT: cmp r3, r1
-; CHECK-NEXT: csel r2, r3, r1, lt
-; CHECK-NEXT: strh r2, [r4], #2
+; CHECK-NEXT: ldrsh r0, [r12], #2
+; CHECK-NEXT: ldrsh r1, [r6], #2
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #15
+; CHECK-NEXT: ssat r0, #16, r0
+; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB6_7
; CHECK-NEXT: .LBB6_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
@@ -1418,23 +1403,16 @@ define arm_aapcs_vfpcc void @ssatmul_8i_q15(i16* nocapture readonly %pSrcA, i16*
; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21
-; CHECK-NEXT: movw r0, #32768
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: movt r0, #65535
-; CHECK-NEXT: movw r1, #32767
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB7_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsh r2, [r12], #2
-; CHECK-NEXT: ldrsh r3, [r6], #2
-; CHECK-NEXT: muls r2, r3, r2
-; CHECK-NEXT: mov r3, r0
-; CHECK-NEXT: cmp.w r0, r2, asr #15
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r3, r2, #15
-; CHECK-NEXT: cmp r3, r1
-; CHECK-NEXT: csel r2, r3, r1, lt
-; CHECK-NEXT: strh r2, [r4], #2
+; CHECK-NEXT: ldrsh r0, [r12], #2
+; CHECK-NEXT: ldrsh r1, [r6], #2
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #15
+; CHECK-NEXT: ssat r0, #16, r0
+; CHECK-NEXT: strh r0, [r4], #2
; CHECK-NEXT: le lr, .LBB7_7
; CHECK-NEXT: .LBB7_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
@@ -2329,8 +2307,7 @@ define arm_aapcs_vfpcc void @ssatmul_8_q7(i8* nocapture readonly %pSrcA, i8* noc
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: beq .LBB14_8
+; CHECK-NEXT: cbz r3, .LBB14_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #7
; CHECK-NEXT: bhi .LBB14_3
@@ -2363,21 +2340,15 @@ define arm_aapcs_vfpcc void @ssatmul_8_q7(i8* nocapture readonly %pSrcA, i8* noc
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: mvn r0, #127
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB14_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsb r1, [r12], #1
-; CHECK-NEXT: ldrsb r2, [r6], #1
-; CHECK-NEXT: muls r1, r2, r1
-; CHECK-NEXT: mvn r2, #127
-; CHECK-NEXT: cmp.w r0, r1, asr #7
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r2, r1, #7
-; CHECK-NEXT: cmp r2, #127
-; CHECK-NEXT: it ge
-; CHECK-NEXT: movge r2, #127
-; CHECK-NEXT: strb r2, [r4], #1
+; CHECK-NEXT: ldrsb r0, [r12], #1
+; CHECK-NEXT: ldrsb r1, [r6], #1
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #7
+; CHECK-NEXT: ssat r0, #8, r0
+; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB14_7
; CHECK-NEXT: .LBB14_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
@@ -2503,21 +2474,15 @@ define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* no
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: mvn r0, #127
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB15_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsb r1, [r12], #1
-; CHECK-NEXT: ldrsb r2, [r6], #1
-; CHECK-NEXT: muls r1, r2, r1
-; CHECK-NEXT: mvn r2, #127
-; CHECK-NEXT: cmp.w r0, r1, asr #7
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r2, r1, #7
-; CHECK-NEXT: cmp r2, #127
-; CHECK-NEXT: it ge
-; CHECK-NEXT: movge r2, #127
-; CHECK-NEXT: strb r2, [r4], #1
+; CHECK-NEXT: ldrsb r0, [r12], #1
+; CHECK-NEXT: ldrsb r1, [r6], #1
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #7
+; CHECK-NEXT: ssat r0, #8, r0
+; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB15_7
; CHECK-NEXT: .LBB15_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
@@ -2640,21 +2605,15 @@ define arm_aapcs_vfpcc void @ssatmul_16i_q7(i8* nocapture readonly %pSrcA, i8* n
; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5
-; CHECK-NEXT: mvn r0, #127
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB16_7: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrsb r1, [r12], #1
-; CHECK-NEXT: ldrsb r2, [r6], #1
-; CHECK-NEXT: muls r1, r2, r1
-; CHECK-NEXT: mvn r2, #127
-; CHECK-NEXT: cmp.w r0, r1, asr #7
-; CHECK-NEXT: it lt
-; CHECK-NEXT: asrlt r2, r1, #7
-; CHECK-NEXT: cmp r2, #127
-; CHECK-NEXT: it ge
-; CHECK-NEXT: movge r2, #127
-; CHECK-NEXT: strb r2, [r4], #1
+; CHECK-NEXT: ldrsb r0, [r12], #1
+; CHECK-NEXT: ldrsb r1, [r6], #1
+; CHECK-NEXT: muls r0, r1, r0
+; CHECK-NEXT: asrs r0, r0, #7
+; CHECK-NEXT: ssat r0, #8, r0
+; CHECK-NEXT: strb r0, [r4], #1
; CHECK-NEXT: le lr, .LBB16_7
; CHECK-NEXT: .LBB16_8: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, r5, r6, pc}
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