[llvm] 96e52c1 - [SVE][CodeGen] Mark ptrue/pfalse instructions as rematerializable

[David Sherwood via llvm-commits]

Author: David Sherwood
Date: 2020-09-21T16:44:32+01:00
New Revision: 96e52c13640ba60417ebd1d03cee79a2c0089308

URL: https://github.com/llvm/llvm-project/commit/96e52c13640ba60417ebd1d03cee79a2c0089308
DIFF: https://github.com/llvm/llvm-project/commit/96e52c13640ba60417ebd1d03cee79a2c0089308.diff

LOG: [SVE][CodeGen] Mark ptrue/pfalse instructions as rematerializable

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/SVEInstrFormats.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index e40598d05742..0d8984b93231 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -277,6 +277,7 @@ class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
   let Inst{3-0}   = Pd;
 
   let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
+  let isReMaterializable = 1;
 }
 
 multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
@@ -499,6 +500,8 @@ class sve_int_pfalse<bits<6> opc, string asm>
   let Inst{9}     = opc{0};
   let Inst{8-4}   = 0b00000;
   let Inst{3-0}   = Pd;
+
+  let isReMaterializable = 1;
 }
 
 class sve_int_ptest<bits<6> opc, string asm>