[PATCH] D87046: [PPC] Do not emit extswsli in 32BIT mode when using -mcpu=pwr9

[Xiangling Liao via Phabricator via llvm-commits]

Xiangling_L added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:16066
       N0.getOperand(0).getValueType() != MVT::i32 ||
       CN1 == nullptr || N->getValueType(0) != MVT::i64)
     return SDValue();
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It seems you can move `Subtarget.isPPC64()` here instead. Since the following code returns `SDValue()` for 32bit no matter what.


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Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:10
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mattr=-altivec -mcpu=pwr9 < %s | FileCheck %s --check-prefix=64BIT
----------------
The failing reason has nothing to do with endian but only related to 32bit or 64bit mode. So I am suggesting you can test `-mtriple=powerpc` and `-mtriple=powerpc64` only


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Comment at: llvm/test/CodeGen/PowerPC/ppc-32bit-shift.ll:17
+  %add = add nsw i32 %inta, %intb
+  %conv = sext i32 %add to i64
+  %shl = shl nsw i64 %conv, 8
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We can simplify the testcase like the following:
define void @a(i32 %add, i64* %sum_a) {
entry:
    %conv = sext i32 %add to i64
    %shl = shl nsw i64 %conv, 8
    store i64 %shl, i64* %sum_a, align 8
    ret void
 }


Repository:
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  https://reviews.llvm.org/D87046/new/

https://reviews.llvm.org/D87046