[PATCH] D87651: [AArch64][SVE] Implement extractelement of i1 vectors.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: paulwalker-arm, sdesmalen, cameron.mcinally.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.
efriedma requested review of this revision.

The implementation just extends the vector to a larger element type, and extracts from that.  Not fancy, but generates reasonable code.

While I'm here, fix warning from computeKnown bits, and implement the obvious patterns for extracting from element zero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87651

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-extract-element.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll

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