[PATCH] D87276: [ARM] Recognize "double extend" reduction patterns

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:14775
+    // long as the bitwidth is high enough to make them equivalent (for example
+    // original v8i16 might be mul at v8i32 and the reduce happens at v8i64).
+    if (ResVT != RetTy)
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A minor followup suggestion: you might want to look at using ComputeNumSignBits etc instead of requiring a specific extension opcode.  This would help if, for example, one of the operands is a constant.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87276/new/

https://reviews.llvm.org/D87276