[llvm] 8e69c3c - [DAGCombiner] Fold fmin/fmax with INF / FLT_MAX
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 14 10:59:46 PDT 2020
Author: Nikita Popov
Date: 2020-09-14T19:59:33+02:00
New Revision: 8e69c3cde8eed94be226bdef1ff6cedda3a33bc4
URL: https://github.com/llvm/llvm-project/commit/8e69c3cde8eed94be226bdef1ff6cedda3a33bc4
DIFF: https://github.com/llvm/llvm-project/commit/8e69c3cde8eed94be226bdef1ff6cedda3a33bc4.diff
LOG: [DAGCombiner] Fold fmin/fmax with INF / FLT_MAX
Similar to D87415, this folds the various float min/max opcodes
with a constant INF or -INF operand, or FLT_MAX / -FLT_MAX operand
if the ninf flag is set. Some of the folds are only possible under
nnan.
The fminnum(X, INF) with nnan and fmaxnum(X, -INF) with nnan cases
are needed to improve the VECREDUCE_FMIN/FMAX lowerings on X86,
the rest is here for the sake of completeness.
Differential Revision: https://reviews.llvm.org/D87571
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/ARM/fminmax-folds.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e4a517601968..48e964c10761 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14037,13 +14037,16 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
}
static SDValue visitFMinMax(SelectionDAG &DAG, SDNode *N,
- APFloat (*Op)(const APFloat &, const APFloat &),
- bool PropagatesNaN) {
+ APFloat (*Op)(const APFloat &, const APFloat &)) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
+ const SDNodeFlags Flags = N->getFlags();
+ unsigned Opc = N->getOpcode();
+ bool PropagatesNaN = Opc == ISD::FMINIMUM || Opc == ISD::FMAXIMUM;
+ bool IsMin = Opc == ISD::FMINNUM || Opc == ISD::FMINIMUM;
if (N0CFP && N1CFP) {
const APFloat &C0 = N0CFP->getValueAPF();
@@ -14054,32 +14057,54 @@ static SDValue visitFMinMax(SelectionDAG &DAG, SDNode *N,
// Canonicalize to constant on RHS.
if (isConstantFPBuildVectorOrConstantFP(N0) &&
!isConstantFPBuildVectorOrConstantFP(N1))
- return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
+ return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Flags);
- // minnum(X, nan) -> X
- // maxnum(X, nan) -> X
- // minimum(X, nan) -> nan
- // maximum(X, nan) -> nan
- if (N1CFP && N1CFP->isNaN())
- return PropagatesNaN ? N->getOperand(1) : N->getOperand(0);
+ if (N1CFP) {
+ const APFloat &AF = N1CFP->getValueAPF();
+
+ // minnum(X, nan) -> X
+ // maxnum(X, nan) -> X
+ // minimum(X, nan) -> nan
+ // maximum(X, nan) -> nan
+ if (AF.isNaN())
+ return PropagatesNaN ? N->getOperand(1) : N->getOperand(0);
+
+ // In the following folds, inf can be replaced with the largest finite
+ // float, if the ninf flag is set.
+ if (AF.isInfinity() || (Flags.hasNoInfs() && AF.isLargest())) {
+ // minnum(X, -inf) -> -inf
+ // maxnum(X, +inf) -> +inf
+ // minimum(X, -inf) -> -inf if nnan
+ // maximum(X, +inf) -> +inf if nnan
+ if (IsMin == AF.isNegative() && (!PropagatesNaN || Flags.hasNoNaNs()))
+ return N->getOperand(1);
+
+ // minnum(X, +inf) -> X if nnan
+ // maxnum(X, -inf) -> X if nnan
+ // minimum(X, +inf) -> X
+ // maximum(X, -inf) -> X
+ if (IsMin != AF.isNegative() && (PropagatesNaN || Flags.hasNoNaNs()))
+ return N->getOperand(0);
+ }
+ }
return SDValue();
}
SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
- return visitFMinMax(DAG, N, minnum, /* PropagatesNaN */ false);
+ return visitFMinMax(DAG, N, minnum);
}
SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
- return visitFMinMax(DAG, N, maxnum, /* PropagatesNaN */ false);
+ return visitFMinMax(DAG, N, maxnum);
}
SDValue DAGCombiner::visitFMINIMUM(SDNode *N) {
- return visitFMinMax(DAG, N, minimum, /* PropagatesNaN */ true);
+ return visitFMinMax(DAG, N, minimum);
}
SDValue DAGCombiner::visitFMAXIMUM(SDNode *N) {
- return visitFMinMax(DAG, N, maximum, /* PropagatesNaN */ true);
+ return visitFMinMax(DAG, N, maximum);
}
SDValue DAGCombiner::visitFABS(SDNode *N) {
diff --git a/llvm/test/CodeGen/ARM/fminmax-folds.ll b/llvm/test/CodeGen/ARM/fminmax-folds.ll
index 30dfd4915d89..b13426c7c050 100644
--- a/llvm/test/CodeGen/ARM/fminmax-folds.ll
+++ b/llvm/test/CodeGen/ARM/fminmax-folds.ll
@@ -65,15 +65,9 @@ define float @test_minnum_const_inf(float %x) {
define float @test_maxnum_const_inf(float %x) {
; CHECK-LABEL: test_maxnum_const_inf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI5_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #32640
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI5_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call float @llvm.maxnum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -97,15 +91,7 @@ define float @test_maximum_const_inf(float %x) {
define float @test_minimum_const_inf(float %x) {
; CHECK-LABEL: test_minimum_const_inf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI7_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI7_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call float @llvm.minimum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -113,15 +99,9 @@ define float @test_minimum_const_inf(float %x) {
define float @test_minnum_const_neg_inf(float %x) {
; CHECK-LABEL: test_minnum_const_neg_inf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI8_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #65408
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI8_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call float @llvm.minnum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -145,15 +125,7 @@ define float @test_maxnum_const_neg_inf(float %x) {
define float @test_maximum_const_neg_inf(float %x) {
; CHECK-LABEL: test_maximum_const_neg_inf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI10_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI10_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call float @llvm.maximum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -177,15 +149,7 @@ define float @test_minimum_const_neg_inf(float %x) {
define float @test_minnum_const_inf_nnan(float %x) {
; CHECK-LABEL: test_minnum_const_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI12_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI12_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.minnum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -193,15 +157,9 @@ define float @test_minnum_const_inf_nnan(float %x) {
define float @test_maxnum_const_inf_nnan(float %x) {
; CHECK-LABEL: test_maxnum_const_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI13_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #32640
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI13_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.maxnum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -209,15 +167,9 @@ define float @test_maxnum_const_inf_nnan(float %x) {
define float @test_maximum_const_inf_nnan(float %x) {
; CHECK-LABEL: test_maximum_const_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI14_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #32640
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI14_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.maximum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -225,15 +177,7 @@ define float @test_maximum_const_inf_nnan(float %x) {
define float @test_minimum_const_inf_nnan(float %x) {
; CHECK-LABEL: test_minimum_const_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI15_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI15_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.minimum.f32(float %x, float 0x7ff0000000000000)
ret float %r
}
@@ -241,15 +185,7 @@ define float @test_minimum_const_inf_nnan(float %x) {
define float @test_minnum_const_inf_nnan_comm(float %x) {
; CHECK-LABEL: test_minnum_const_inf_nnan_comm:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI16_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI16_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.minnum.f32(float 0x7ff0000000000000, float %x)
ret float %r
}
@@ -257,15 +193,9 @@ define float @test_minnum_const_inf_nnan_comm(float %x) {
define float @test_maxnum_const_inf_nnan_comm(float %x) {
; CHECK-LABEL: test_maxnum_const_inf_nnan_comm:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI17_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #32640
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI17_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.maxnum.f32(float 0x7ff0000000000000, float %x)
ret float %r
}
@@ -273,15 +203,9 @@ define float @test_maxnum_const_inf_nnan_comm(float %x) {
define float @test_maximum_const_inf_nnan_comm(float %x) {
; CHECK-LABEL: test_maximum_const_inf_nnan_comm:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI18_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #32640
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI18_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.maximum.f32(float 0x7ff0000000000000, float %x)
ret float %r
}
@@ -289,15 +213,7 @@ define float @test_maximum_const_inf_nnan_comm(float %x) {
define float @test_minimum_const_inf_nnan_comm(float %x) {
; CHECK-LABEL: test_minimum_const_inf_nnan_comm:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI19_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI19_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan float @llvm.minimum.f32(float 0x7ff0000000000000, float %x)
ret float %r
}
@@ -305,16 +221,7 @@ define float @test_minimum_const_inf_nnan_comm(float %x) {
define <2 x float> @test_minnum_const_inf_nnan_comm_vec(<2 x float> %x) {
; CHECK-LABEL: test_minnum_const_inf_nnan_comm_vec:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, .LCPI20_0
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vminnm.f32 d16, d17, d16
-; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI20_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan <2 x float> @llvm.minnum.v2f32(<2 x float> <float 0x7ff0000000000000, float 0x7ff0000000000000>, <2 x float> %x)
ret <2 x float> %r
}
@@ -323,8 +230,6 @@ define <2 x float> @test_maxnum_const_inf_nnan_comm_vec(<2 x float> %x) {
; CHECK-LABEL: test_maxnum_const_inf_nnan_comm_vec:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, .LCPI21_0
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vmaxnm.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 3
@@ -340,8 +245,6 @@ define <2 x float> @test_maximum_const_inf_nnan_comm_vec(<2 x float> %x) {
; CHECK-LABEL: test_maximum_const_inf_nnan_comm_vec:
; CHECK: @ %bb.0:
; CHECK-NEXT: vldr d16, .LCPI22_0
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vmax.f32 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 3
@@ -356,16 +259,7 @@ define <2 x float> @test_maximum_const_inf_nnan_comm_vec(<2 x float> %x) {
define <2 x float> @test_minimum_const_inf_nnan_comm_vec(<2 x float> %x) {
; CHECK-LABEL: test_minimum_const_inf_nnan_comm_vec:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr d16, .LCPI23_0
-; CHECK-NEXT: vmov d17, r0, r1
-; CHECK-NEXT: vmin.f32 d16, d17, d16
-; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI23_0:
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
-; CHECK-NEXT: .long 0x7f800000 @ float +Inf
%r = call nnan <2 x float> @llvm.minimum.v2f32(<2 x float> <float 0x7ff0000000000000, float 0x7ff0000000000000>, <2 x float> %x)
ret <2 x float> %r
}
@@ -373,15 +267,9 @@ define <2 x float> @test_minimum_const_inf_nnan_comm_vec(<2 x float> %x) {
define float @test_minnum_const_neg_inf_nnan(float %x) {
; CHECK-LABEL: test_minnum_const_neg_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI24_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #65408
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI24_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call nnan float @llvm.minnum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -389,15 +277,7 @@ define float @test_minnum_const_neg_inf_nnan(float %x) {
define float @test_maxnum_const_neg_inf_nnan(float %x) {
; CHECK-LABEL: test_maxnum_const_neg_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI25_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI25_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call nnan float @llvm.maxnum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -405,15 +285,7 @@ define float @test_maxnum_const_neg_inf_nnan(float %x) {
define float @test_maximum_const_neg_inf_nnan(float %x) {
; CHECK-LABEL: test_maximum_const_neg_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI26_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI26_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call nnan float @llvm.maximum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -421,15 +293,9 @@ define float @test_maximum_const_neg_inf_nnan(float %x) {
define float @test_minimum_const_neg_inf_nnan(float %x) {
; CHECK-LABEL: test_minimum_const_neg_inf_nnan:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI27_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #0
+; CHECK-NEXT: movt r0, #65408
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI27_0:
-; CHECK-NEXT: .long 0xff800000 @ float -Inf
%r = call nnan float @llvm.minimum.f32(float %x, float 0xfff0000000000000)
ret float %r
}
@@ -581,15 +447,9 @@ define float @test_minnum_const_max_ninf(float %x) {
define float @test_maxnum_const_max_ninf(float %x) {
; CHECK-LABEL: test_maxnum_const_max_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI37_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #65535
+; CHECK-NEXT: movt r0, #32639
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI37_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call ninf float @llvm.maxnum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -613,15 +473,7 @@ define float @test_maximum_const_max_ninf(float %x) {
define float @test_minimum_const_max_ninf(float %x) {
; CHECK-LABEL: test_minimum_const_max_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI39_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI39_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call ninf float @llvm.minimum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -629,15 +481,8 @@ define float @test_minimum_const_max_ninf(float %x) {
define float @test_minnum_const_neg_max_ninf(float %x) {
; CHECK-LABEL: test_minnum_const_neg_max_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI40_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mvn r0, #8388608
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI40_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call ninf float @llvm.minnum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
@@ -661,15 +506,7 @@ define float @test_maxnum_const_neg_max_ninf(float %x) {
define float @test_maximum_const_neg_max_ninf(float %x) {
; CHECK-LABEL: test_maximum_const_neg_max_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI42_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI42_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call ninf float @llvm.maximum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
@@ -693,15 +530,7 @@ define float @test_minimum_const_neg_max_ninf(float %x) {
define float @test_minnum_const_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_minnum_const_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI44_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI44_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call nnan ninf float @llvm.minnum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -709,15 +538,9 @@ define float @test_minnum_const_max_nnan_ninf(float %x) {
define float @test_maxnum_const_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_maxnum_const_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI45_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #65535
+; CHECK-NEXT: movt r0, #32639
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI45_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call nnan ninf float @llvm.maxnum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -725,15 +548,9 @@ define float @test_maxnum_const_max_nnan_ninf(float %x) {
define float @test_maximum_const_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_maximum_const_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI46_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: movw r0, #65535
+; CHECK-NEXT: movt r0, #32639
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI46_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call nnan ninf float @llvm.maximum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -741,15 +558,7 @@ define float @test_maximum_const_max_nnan_ninf(float %x) {
define float @test_minimum_const_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_minimum_const_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI47_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI47_0:
-; CHECK-NEXT: .long 0x7f7fffff @ float 3.40282347E+38
%r = call nnan ninf float @llvm.minimum.f32(float %x, float 0x47efffffe0000000)
ret float %r
}
@@ -757,15 +566,8 @@ define float @test_minimum_const_max_nnan_ninf(float %x) {
define float @test_minnum_const_neg_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_minnum_const_neg_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI48_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vminnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mvn r0, #8388608
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI48_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call nnan ninf float @llvm.minnum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
@@ -773,15 +575,7 @@ define float @test_minnum_const_neg_max_nnan_ninf(float %x) {
define float @test_maxnum_const_neg_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_maxnum_const_neg_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI49_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmaxnm.f32 s0, s2, s0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI49_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call nnan ninf float @llvm.maxnum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
@@ -789,15 +583,7 @@ define float @test_maxnum_const_neg_max_nnan_ninf(float %x) {
define float @test_maximum_const_neg_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_maximum_const_neg_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI50_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmax.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI50_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call nnan ninf float @llvm.maximum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
@@ -805,15 +591,8 @@ define float @test_maximum_const_neg_max_nnan_ninf(float %x) {
define float @test_minimum_const_neg_max_nnan_ninf(float %x) {
; CHECK-LABEL: test_minimum_const_neg_max_nnan_ninf:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vldr s0, .LCPI51_0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: vmin.f32 d0, d1, d0
-; CHECK-NEXT: vmov r0, s0
+; CHECK-NEXT: mvn r0, #8388608
; CHECK-NEXT: bx lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI51_0:
-; CHECK-NEXT: .long 0xff7fffff @ float -3.40282347E+38
%r = call nnan ninf float @llvm.minimum.f32(float %x, float 0xc7efffffe0000000)
ret float %r
}
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