[PATCH] D87071: [Scheduling] Add a mutation to schedule GOT indirect instructions close to each other for linker optimization

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll:26
 ; CHECK-NEXT:    pstd r4, FuncLocal at PCREL(0), 1
+; CHECK-NEXT:    std r4, 0(r3)
 ; CHECK-NEXT:    blr
----------------
std and pstd is not aliased. We can still do the linker opt for it but now, we can't as peephole didn't know they are not aliased. Further, we didn't emit the symbol because we have uses in-between pld and std which is too conservative also. If the other instr is store, we won't have problems if there is any uses in-between the pair. 


Repository:
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  https://reviews.llvm.org/D87071/new/

https://reviews.llvm.org/D87071