[llvm] e8e3693 - Change range operator from deprecated '-' to '...'

[Paul C. Anagnostopoulos via llvm-commits]

Author: Paul C. Anagnostopoulos
Date: 2020-09-12T16:26:32-04:00
New Revision: e8e3693ceaa1afe267f21d2ba8d9565ea8fe7c12

URL: https://github.com/llvm/llvm-project/commit/e8e3693ceaa1afe267f21d2ba8d9565ea8fe7c12
DIFF: https://github.com/llvm/llvm-project/commit/e8e3693ceaa1afe267f21d2ba8d9565ea8fe7c12.diff

LOG: Change range operator from deprecated '-' to '...'

Added: 
    

Modified: 
    llvm/test/TableGen/AllowDuplicateRegisterNames.td
    llvm/test/TableGen/BigEncoder.td
    llvm/test/TableGen/BitOffsetDecoder.td
    llvm/test/TableGen/BitsInit.td

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/AllowDuplicateRegisterNames.td b/llvm/test/TableGen/AllowDuplicateRegisterNames.td
index 2ba63c434ca5..897a628fe64b 100644
--- a/llvm/test/TableGen/AllowDuplicateRegisterNames.td
+++ b/llvm/test/TableGen/AllowDuplicateRegisterNames.td
@@ -27,7 +27,7 @@ class ArchReg<string n, list <string> alt, list <RegAltNameIndex> altidx>
 
 def ABIRegAltName : RegAltNameIndex;
 
-foreach i = 0-3 in {
+foreach i = 0...3 in {
   def R#i#_32 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName]>;
   def R#i#_64 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName]>;
 }

diff  --git a/llvm/test/TableGen/BigEncoder.td b/llvm/test/TableGen/BigEncoder.td
index 5c4bc016e269..9b9d38243350 100644
--- a/llvm/test/TableGen/BigEncoder.td
+++ b/llvm/test/TableGen/BigEncoder.td
@@ -19,8 +19,8 @@ def foo : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<65> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xAA;
-    let Inst{14-8} = factor{6-0}; // no offset
+    let Inst{7...0} = 0xAA;
+    let Inst{14...8} = factor{6...0}; // no offset
     let AsmString = "foo  $factor";
     field bits<16> SoftFail = 0;
     }
@@ -29,8 +29,8 @@ def bar : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<65> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xBB;
-    let Inst{15-8} = factor{10-3}; // offset by 3
+    let Inst{7...0} = 0xBB;
+    let Inst{15...8} = factor{10...3}; // offset by 3
     let AsmString = "bar  $factor";
     field bits<16> SoftFail = 0;
     }
@@ -39,8 +39,8 @@ def biz : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<65> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xCC;
-    let Inst{11-8,15-12} = factor{10-3}; // offset by 3, multipart
+    let Inst{7...0} = 0xCC;
+    let Inst{11...8,15...12} = factor{10...3}; // offset by 3, multipart
     let AsmString = "biz  $factor";
     field bits<16> SoftFail = 0;
     }

diff  --git a/llvm/test/TableGen/BitOffsetDecoder.td b/llvm/test/TableGen/BitOffsetDecoder.td
index a928664398f0..f94e8d4f0978 100644
--- a/llvm/test/TableGen/BitOffsetDecoder.td
+++ b/llvm/test/TableGen/BitOffsetDecoder.td
@@ -19,8 +19,8 @@ def foo : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<16> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xAA;
-    let Inst{14-8} = factor{6-0}; // no offset
+    let Inst{7...0} = 0xAA;
+    let Inst{14...8} = factor{6...0}; // no offset
     let AsmString = "foo  $factor";
     field bits<16> SoftFail = 0;
     }
@@ -29,8 +29,8 @@ def bar : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<16> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xBB;
-    let Inst{15-8} = factor{10-3}; // offset by 3
+    let Inst{7...0} = 0xBB;
+    let Inst{15...8} = factor{10...3}; // offset by 3
     let AsmString = "bar  $factor";
     field bits<16> SoftFail = 0;
     }
@@ -39,8 +39,8 @@ def biz : Instruction {
     let InOperandList = (ins i32imm:$factor);
     field bits<16> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xCC;
-    let Inst{11-8,15-12} = factor{10-3}; // offset by 3, multipart
+    let Inst{7...0} = 0xCC;
+    let Inst{11...8,15...12} = factor{10...3}; // offset by 3, multipart
     let AsmString = "biz  $factor";
     field bits<16> SoftFail = 0;
     }
@@ -49,8 +49,8 @@ def baz : Instruction {
     let InOperandList = (ins Myi32:$factor);
     field bits<16> Inst;
     bits<32> factor;
-    let Inst{7-0} = 0xDD;
-    let Inst{15-8} = factor{11-4}; // offset by 4 + custom decode
+    let Inst{7...0} = 0xDD;
+    let Inst{15...8} = factor{11...4}; // offset by 4 + custom decode
     let AsmString = "baz  $factor";
     field bits<16> SoftFail = 0;
     }

diff  --git a/llvm/test/TableGen/BitsInit.td b/llvm/test/TableGen/BitsInit.td
index 16d2d07753ad..6f9acd346ba8 100644
--- a/llvm/test/TableGen/BitsInit.td
+++ b/llvm/test/TableGen/BitsInit.td
@@ -38,7 +38,7 @@ def {
   bits<2> D8 = { 0 };    // type mismatch.  RHS doesn't have enough bits
 
   bits<8> E;
-  let E{7-0} = {0,0,1,?,?,?,?,?};
+  let E{7..0} = {0,0,1,?,?,?,?,?};
   let E{3-0} = 0b0010;
 
   bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok