[PATCH] D87209: [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 291349.
craig.topper added a comment.

-Run clang-format
-Remove Size variable from X86 code and just use VT.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87209/new/

https://reviews.llvm.org/D87209

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/parity.ll
  llvm/test/CodeGen/ARM/parity.ll
  llvm/test/CodeGen/X86/parity.ll
  llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll

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