[PATCH] D46884: [AArch64] Cortex-A55 scheduler model

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: lib/Target/AArch64/AArch64SchedA55.td:160
+                                                     let ResourceCycles = [14]; }
+def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 33;
+                                                     let ResourceCycles = [29]; }
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evgeny777 wrote:
> @SjoerdMeijer Latency/hazard for FDivDP seem to not match those in optimization guide for Cortex-A55 (should be 22/19). Why's that? There are mismatches in other places also (for instance WriteLD should (?) be 3 cycles, not 4)
Just for a bit of context, I put this scheduler up for review to share it so people could pick it up. We knew it needed some more tuning (but we didn't have the bandwidth), which was confirmed with some benchmarks, see some earlier messages.

I haven't checked, but I assume you're right about those latencies. I am guessing they were oversights. For the FDivDP case, which its long latency, I am not sure it would make a practical difference though, but anyway. And for the WriteLD, it may be the case that this was giving better performance (schedmodels are not always an exact science), but it may have been a typo too.

If you plan to improve this, I would be happy to support this with reviews etc. and see if we can get this committed.

 


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https://reviews.llvm.org/D46884