[PATCH] D87149: [InstCombine] erase instructions leading up to unreachable

[Nuno Lopes via Phabricator via llvm-commits]

nlopes added a comment.

Ok, let me make it more concrete.
it seems we have 3 possible semantics:

1. volatile accesses never trap, but rather trigger UB when the address is not dereferenceable
2. they trap if the address is not dereferenceable
3. they may trap regardless (i.e., they can never be removed). Alternatively we can state that the load/store address traces are externally observable and can't change

Regular accesses follow semantics 1).
Option 3) makes me uncomfortable. Proving refinement of that is non-trivial and I'm scared of the implications. I can study that option is there's demand.
Option 2) seems reasonable to me if needed to make LLVM nicer for some applications.


Repository:
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https://reviews.llvm.org/D87149