[PATCH] D87430: [ARM] Add heuristic to avoid lowering calls to blx for Thumb1 in ARMTargetLowering::LowerCall

[Prathamesh via Phabricator via llvm-commits]

prathamesh created this revision.
prathamesh added a reviewer: dmgreen.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
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prathamesh requested review of this revision.

Hi,
This is a follow-up on https://reviews.llvm.org/D79785.
This patch implements a heuristic to avoid lowering calls to blx if MF.getFunction().arg_size() + Outs.size() < (number of registers) - 1, since we need at least one register for holding function's address. It converts all calls to bl for the attached test-case. However it might not be able to detect cases when we need more than one register to compute arguments. For that, the approach in D79785 <https://reviews.llvm.org/D79785>, can catch some of these, by folding tLDRpci, tBLXr -> tBL.
Does this patch look reasonable ?
Testing with make check-llvm with -DLLVM_ENABLE_EXPENSIVE_CHECKS=ON shows no unexpected failures.

I have a couple of questions:
(a) How do we get number of available registers for subtarget in LowerCall ?
(b) I assume Outs.size() will correspond to number of arguments passed to the function ?
TargetLowering.h has following comment above LowerCall():

  /// The outgoing arguments to the call are described by the Outs array,
  /// and the values to be returned by the call are described by the Ins

/// array.

Thanks!


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87430

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/minsize-call-cse-2.ll


Index: llvm/test/CodeGen/ARM/minsize-call-cse-2.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/minsize-call-cse-2.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv6m-arm-none-eabi"
+
+; CHECK-LABEL: f:
+; CHECK: bl g
+; CHECK: bl g
+; CHECK: bl g
+; CHECK: bl g
+define void @f(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a) optsize minsize  {
+entry:
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  call void @g(i32* %p, i32 %x, i32 %y, i32 %z, i32 %a)
+  ret void
+}
+
+declare void @g(i32*,i32,i32,i32,i32)
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2255,6 +2255,15 @@
                          return isa<Instruction>(U) &&
                                 cast<Instruction>(U)->getParent() == BB;
                        }) > 2;
+
+      // FIXME: How to obtain number of available registers ?
+      // Hardcoded for now.
+      unsigned nRegs = 7;
+
+      // Check that there is at least one register available for holding
+      // function's address
+      if (PreferIndirect && Subtarget->isThumb1Only())
+        PreferIndirect = MF.getFunction().arg_size() + Outs.size() < nRegs - 1;
     }
   }
   if (isTailCall) {


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