[llvm] 5a4a05c - [ARM] Add additional fmin/fmax with nan tests (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2020-09-09T23:53:32+02:00
New Revision: 5a4a05c8116ebdcb434cd15796a255cf024a6bf0

URL: https://github.com/llvm/llvm-project/commit/5a4a05c8116ebdcb434cd15796a255cf024a6bf0
DIFF: https://github.com/llvm/llvm-project/commit/5a4a05c8116ebdcb434cd15796a255cf024a6bf0.diff

LOG: [ARM] Add additional fmin/fmax with nan tests (NFC)

Adding these to ARM which has both FMINNUM and FMINIMUM.

Added: 
    llvm/test/CodeGen/ARM/fminmax-folds.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/ARM/fminmax-folds.ll b/llvm/test/CodeGen/ARM/fminmax-folds.ll
new file mode 100644
index 000000000000..807c0a8b8eb4
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fminmax-folds.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=armv8-eabi | FileCheck %s
+
+declare float @llvm.minnum.f32(float, float)
+declare float @llvm.maxnum.f32(float, float)
+declare float @llvm.minimum.f32(float, float)
+declare float @llvm.maximum.f32(float, float)
+
+define float @test_minnum_const_nan(float %x) {
+; CHECK-LABEL: test_minnum_const_nan:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr s0, .LCPI0_0
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vminnm.f32 s0, s2, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI0_0:
+; CHECK-NEXT:    .long 0x7ff80000 @ float NaN
+  %r = call float @llvm.minnum.f32(float %x, float 0x7fff000000000000)
+  ret float %r
+}
+
+define float @test_maxnum_const_nan(float %x) {
+; CHECK-LABEL: test_maxnum_const_nan:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr s0, .LCPI1_0
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vmaxnm.f32 s0, s2, s0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI1_0:
+; CHECK-NEXT:    .long 0x7ff80000 @ float NaN
+  %r = call float @llvm.maxnum.f32(float %x, float 0x7fff000000000000)
+  ret float %r
+}
+
+define float @test_maximum_const_nan(float %x) {
+; CHECK-LABEL: test_maximum_const_nan:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr s0, .LCPI2_0
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vmax.f32 d0, d1, d0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI2_0:
+; CHECK-NEXT:    .long 0x7ff80000 @ float NaN
+  %r = call float @llvm.maximum.f32(float %x, float 0x7fff000000000000)
+  ret float %r
+}
+
+define float @test_minimum_const_nan(float %x) {
+; CHECK-LABEL: test_minimum_const_nan:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr s0, .LCPI3_0
+; CHECK-NEXT:    vmov s2, r0
+; CHECK-NEXT:    vmin.f32 d0, d1, d0
+; CHECK-NEXT:    vmov r0, s0
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI3_0:
+; CHECK-NEXT:    .long 0x7ff80000 @ float NaN
+  %r = call float @llvm.minimum.f32(float %x, float 0x7fff000000000000)
+  ret float %r
+}