[llvm] 0ee54cf - [Hexagon] Account for truncating pairs to non-pairs when widening truncates

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2020-09-09T14:31:52-05:00
New Revision: 0ee54cf88329c50f25872ac1c67d7ae60ee3154c

URL: https://github.com/llvm/llvm-project/commit/0ee54cf88329c50f25872ac1c67d7ae60ee3154c
DIFF: https://github.com/llvm/llvm-project/commit/0ee54cf88329c50f25872ac1c67d7ae60ee3154c.diff

LOG: [Hexagon] Account for truncating pairs to non-pairs when widening truncates

Added missing selection patterns for vpackl.

Added: 
    llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatternsHVX.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index c9435cd21c2e..630fd7a17040 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -406,9 +406,15 @@ let Predicates = [UseHVX] in {
   def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
 
+  // Vpackl is a pseudo-op that is used when legalizing widened truncates.
+  // It should never be produced with a register pair in the output, but
+  // it can happen to have a pair as an input.
   def: Pat<(VecI8  (vpackl HVI16:$Vs)), (V6_vdealb HvxVR:$Vs)>;
   def: Pat<(VecI8  (vpackl HVI32:$Vs)), (V6_vdealb4w (IMPLICIT_DEF), HvxVR:$Vs)>;
   def: Pat<(VecI16 (vpackl HVI32:$Vs)), (V6_vdealh HvxVR:$Vs)>;
+  def: Pat<(VecI8  (vpackl HWI16:$Vs)), (V6_vpackeb (HiVec $Vs), (LoVec $Vs))>;
+  def: Pat<(VecI8  (vpackl HWI32:$Vs)), (V6_vdealb4w (HiVec $Vs), (LoVec $Vs))>;
+  def: Pat<(VecI16 (vpackl HWI32:$Vs)), (V6_vpackeh (HiVec $Vs), (LoVec $Vs))>;
 
   def: Pat<(VecI16 (bswap HVI16:$Vs)),
            (V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;

diff  --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
new file mode 100644
index 000000000000..83d49fca03b8
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-widen-truncate-pair.ll
@@ -0,0 +1,16 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This has a v32i8 = truncate v16i32 (64b mode), which was legalized to
+; 64i8 = vpackl v32i32, for which there were no selection patterns provided.
+; Check that we generate vdeale for this.
+
+; CHECK-LABEL: fred:
+; CHECK: vdeale(v1.b,v0.b)
+define void @fred(<32 x i8>* %a0, <32 x i32> %a1) #0 {
+  %v0 = trunc <32 x i32> %a1 to <32 x i8>
+  store <32 x i8> %v0, <32 x i8>* %a0, align 32
+  ret void
+}
+
+attributes #0 = { "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length64b" }
+