[PATCH] D87397: [AArch64][GlobalISel] Share address mode selection code for memops

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
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We were missing support for the G_ADD_LOW + ADRP folding optimization in the manual selection code for G_LOAD, G_STORE, and G_ZEXTLOAD.

As a result, we were missing cases like this, where we don't import a pattern (or no pattern exists)

  @foo = external hidden global i32*
  define void @baz(i32* %0) {
  store i32* %0, i32** @foo
  ret void
  }

https://godbolt.org/z/16r7ad

This functionality already existed in the addressing mode functions for the importer. So, this patch makes the manual selection code use `selectAddrModeIndexed` rather than duplicating work.

This is a 0.2% geomean code size improvement for CTMark at -O3.

There is one code size increase (0.1% on lencod) which is likely because `selectAddrModeIndexed` doesn't look through constants right now.


https://reviews.llvm.org/D87397

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir

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