[PATCH] D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12989-12990
+    return DAG.getUNDEF(ResVT);
+  else if (Op.getOpcode() == AArch64ISD::UZP1)
+    return Op->getOperand(N->getOpcode() == AArch64ISD::UUNPKHI ? 1 : 0);
+
----------------
In it's current form I don't think this is correct.  The UUNPK instructions zero the even lanes and so you need to ensure the chosen child of the UZP1 honours this requirement.  Do you know the exact sequence you expect to see?  For example perhaps the pattern you're after is `UUNPKLO(UZP1(UUNPKLO(X), ??)) -> UUNPKLO(X)` or some `UZP1(UUNPKLO(UZP1(X,Y))... ->UZP1(X,Y)` like sequence. 


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8949
+    if (!Op0VT.isInteger() || !Op1VT.isInteger())
+      return SDValue();
+
----------------
efriedma wrote:
> Do we need to check the result type is legal?
As well as what Eli asked I also don't think InVT.isInteger is required because by INSERT_SUBVECTOR's definition the subvector must have the same element type as the result vector.


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  https://reviews.llvm.org/D86548/new/

https://reviews.llvm.org/D86548