[PATCH] D87108: [ImplicitNullCheck] Handle instructions that do not modify null behaviour of null checked reg

[Anna Thomas via Phabricator via llvm-commits]

anna added inline comments.


================
Comment at: llvm/test/CodeGen/X86/implicit-null-check.ll:623
+   ret i64 %t
+}
 !0 = !{}
----------------
anna wrote:
> reames wrote:
> > Please add a couple of counter examples.  Particularly:
> > %rax = shift %rdx, %rax  (i.e. wrong operand order)
> > %rax = add64ri %rax, 1 (i.e. a different instruction)
> > 
> wrong operand order for shift doesn't work (see above comment about rr variant). will add the different instruction case.
I might have to play around with the IR to get the %rax "ri" form working the way we want, i.e. don't convert to implicit null check. Today the "add ri" form doesn't exist before implicit null check. X86 does a pretty decent job and  patterns such as "add immediate OR shift, add immediate" is converted into complex addressing mode load. 
For example IR such as:
```
not_null:
+    %y = ptrtoint i64* %x to i64 
+    %shry = shl i64 %y, 6
+    %shry.add = add i64 %shry, 1
+    %y.ptr = inttoptr i64 %shry.add to i64*
+    %x.loc = getelementptr i64, i64* %y.ptr, i64 1
+    %t = load i64, i64* %x.loc
+    ret i64 %t
```

becomes this before implicit-null-checks:
```
 liveins: $rdi
  renamable $rdi = SHL64ri killed renamable $rdi(tied-def 0), 6, implicit-def dead $eflags
  renamable $rax = MOV64rm killed renamable $rdi, 1, $noreg, 9, $noreg :: (load 8 from %ir.x.loc) <-- rax = rdi + 1 * 0 + 9 
  RETQ $rax
```
where rdi is the ZeroValueReg.

So, I'm adding an "rr" form and that works as a counter example. 


Repository:
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  https://reviews.llvm.org/D87108/new/

https://reviews.llvm.org/D87108