[PATCH] D86952: [MIRVRegNamer] MachineInstr StableHashing.

[Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7fff1fbd3ce1: [MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo) (authored by plotfi, committed by Puyan Lotfi <plotfi at fb.com>).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86952/new/

https://reviews.llvm.org/D86952

Files:
  llvm/include/llvm/CodeGen/MachineOperand.h
  llvm/include/llvm/CodeGen/MachineStableHash.h
  llvm/include/llvm/CodeGen/StableHashing.h
  llvm/lib/CodeGen/CMakeLists.txt
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineStableHash.cpp
  llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
  llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir
  llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
  llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
  llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
  llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
  llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
  llvm/test/CodeGen/MIR/Generic/CFPImmMIRCanonHash.mir
  llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir
  llvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir
  llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

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