[PATCH] D86601: [LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

@foad I managed to reduce the test case to this:

llc -mtriple=sparcv9--

  define i32 @PR47303() {
  bb:
    %i = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> undef, <4 x i64> undef, <4 x i64> <i64 57, i64 27, i64 12, i64 33>)
    %i1 = add <4 x i64> %i, zeroinitializer
    %i2 = add <4 x i64> %i1, zeroinitializer
    %i3 = extractelement <4 x i64> %i2, i32 0
    %i4 = add i64 0, %i3
    %i5 = xor i64 0, %i4
    %i6 = trunc i64 %i5 to i32
    %i7 = mul i32 %i6, 797982799
    ret i32 %i7
  }
  declare <4 x i64> @llvm.fshl.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)


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