[PATCH] D85364: [SVE][WIP] Implement lowering for fixed width select

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a subscriber: t.p.northover.
cameron.mcinally added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7257
 
-    assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
+    assert(SrcVT.getSizeInBits() <= 4 * VT.getSizeInBits());
 
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@t.p.northover, does this change look okay to you? I suspect that this assert is assuming we only have NEON 64b and 128b vectors.

Fixed width SVE now has larger vectors, and for these particular tests we want to extract a 1/4 width subvector from a single width vector.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9045
+      InVT.getSizeInBits() == 128)
     return Op;
 
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Just checking if anyone sees a problem with this change. We need to explicitly check that this is a 128b vector now, since SVE can see larger fixed width vectors.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85364/new/

https://reviews.llvm.org/D85364