[PATCH] D87032: [AMDGPU] Remove the dead spill slots while spilling FP/BP to memory

[Venkata Ramanaiah Nalamothu via Phabricator via llvm-commits]

RamNalamothu created this revision.
RamNalamothu added reviewers: kerbowa, arsenm, scott.linder.
Herald added subscribers: llvm-commits, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
Herald added a project: LLVM.
RamNalamothu requested review of this revision.
Herald added a subscriber: wdng.

During the PEI pass, the dead TargetStackID::SGPRSpill spill slots
are not being removed while spilling the FP/BP to memory.

Fixes: SWDEV-250393


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D87032

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/stack-realign.ll


Index: llvm/test/CodeGen/AMDGPU/stack-realign.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -291,12 +291,12 @@
 ; GCN-LABEL: spill_bp_to_memory_scratch_reg_needed_mubuf_offset
 ; GCN: s_or_saveexec_b64 s[4:5], -1
 ; GCN: v_mov_b32_e32 v0, s33
-; GCN-NOT: v_mov_b32_e32 v0, 0x1088
-; GCN-NEXT: v_mov_b32_e32 v1, 0x1088
+; GCN-NOT: v_mov_b32_e32 v0, 0x1084
+; GCN-NEXT: v_mov_b32_e32 v1, 0x1084
 ; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], s32 offen
 ; GCN: v_mov_b32_e32 v0, s34
-; GCN-NOT: v_mov_b32_e32 v0, 0x1090
-; GCN-NEXT: v_mov_b32_e32 v1, 0x1090
+; GCN-NOT: v_mov_b32_e32 v0, 0x1088
+; GCN-NEXT: v_mov_b32_e32 v1, 0x1088
 ; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], s32 offen
   %local_val = alloca i32, align 128, addrspace(5)
   store volatile i32 %b, i32 addrspace(5)* %local_val, align 128
Index: llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+++ llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
@@ -529,8 +529,8 @@
 ; GCN-LABEL: {{^}}spill_fp_to_memory_scratch_reg_needed_mubuf_offset
 ; GCN: s_or_saveexec_b64 s[4:5], -1
 ; GCN: v_mov_b32_e32 v0, s33
-; GCN-NOT: v_mov_b32_e32 v0, 0x100c
-; GCN-NEXT: v_mov_b32_e32 v1, 0x100c
+; GCN-NOT: v_mov_b32_e32 v0, 0x1008
+; GCN-NEXT: v_mov_b32_e32 v1, 0x1008
 ; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], s32 offen
 define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval align 4 %arg) #3 {
   %alloca = alloca i32, addrspace(5)
Index: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -112,15 +112,19 @@
       // 3: There's no free lane to spill, and no free register to save FP/BP,
       // so we're forced to spill another VGPR to use for the spill.
       FrameIndex = NewFI;
+
+      LLVM_DEBUG(
+          auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
+          dbgs() << (IsFP ? "FP" : "BP") << " requires fallback spill to "
+                 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';);
     } else {
+      // Remove dead <NewFI> index
+      MF.getFrameInfo().RemoveStackObject(NewFI);
       // 4: If all else fails, spill the FP/BP to memory.
       FrameIndex = FrameInfo.CreateSpillStackObject(4, Align(4));
+      LLVM_DEBUG(dbgs() << "Reserved FI " << FrameIndex << " for spilling "
+                        << (IsFP ? "FP" : "BP") << "\n");
     }
-
-    LLVM_DEBUG(auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
-               dbgs() << (IsFP ? "FP" : "BP") << " requires fallback spill to "
-                      << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane
-                      << '\n';);
   } else {
     LLVM_DEBUG(dbgs() << "Saving " << (IsFP ? "FP" : "BP") << " with copy to "
                       << printReg(TempSGPR, TRI) << '\n');


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