[PATCH] D86548: [SVE][CodeGen] Legalisation of truncate for scalable vectors

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9082
+    else if (Vec0.getOpcode() == AArch64ISD::UZP1)
+      HalfVec0 = Vec0->getOperand(0);
+    else {
----------------
efriedma wrote:
> `Vec0->getOperand(0);` looks wrong; should it be `Vec0->getOperand(Idx == 0 ? 0 : 1)`?
I think it should be
```
Vec0->getOperand(Idx == 0 ? 1 : 0)
```
since we want to keep lower half when inserting a subvec into the upper half and vice-versa.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86548/new/

https://reviews.llvm.org/D86548