[PATCH] D86952: [MIRVRegNamer] MachineInstr StableHashing.

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi created this revision.
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Introducing Stable Hashing, based on Fowler–Noll–Vo hash function.
This hashing scheme has been useful out of tree, and I want to start experimenting with it.
Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner.

This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer).
We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86952

Files:
  llvm/include/llvm/CodeGen/MachineStableHash.h
  llvm/include/llvm/CodeGen/StableHashing.h
  llvm/lib/CodeGen/CMakeLists.txt
  llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineStableHash.cpp
  llvm/test/CodeGen/MIR/AArch64/addrspace-memoperands.mir
  llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir
  llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
  llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
  llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
  llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
  llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
  llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
  llvm/test/CodeGen/MIR/Generic/CFPImmMIRCanonHash.mir
  llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir
  llvm/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir
  llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

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