[PATCH] D86878: [AMDGPU] Fix a miscompile in add combine

[Piotr Sobczak via Phabricator via llvm-commits]

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The Add/Sub combine removes a zext when present on a boolean operation,
which is not safe if the resultant addcarry stays in sgpr (is not
moved to vgpr during si-fix-sgpr-copies). In the abscence of v_cndmask
that is normally generated for such an zext, the resultant vcc can have
bits set for inactive lanes which can produce wrong results.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86878

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
  llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll

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