[llvm] 3c8be94 - [NFC][ARM] Add tail predication test
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 05:46:37 PDT 2020
Author: Sam Parker
Date: 2020-08-28T13:46:10+01:00
New Revision: 3c8be94f3d8a82f07f61aeddf834a8cc007175bb
URL: https://github.com/llvm/llvm-project/commit/3c8be94f3d8a82f07f61aeddf834a8cc007175bb
DIFF: https://github.com/llvm/llvm-project/commit/3c8be94f3d8a82f07f61aeddf834a8cc007175bb.diff
LOG: [NFC][ARM] Add tail predication test
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
new file mode 100644
index 000000000000..f013cb2f8615
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
@@ -0,0 +1,930 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
+
+--- |
+ define dso_local arm_aapcs_vfpcc i32 @mul_var_i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
+ entry:
+ %cmp9.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv14 = phi i8* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %15, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv13 = bitcast i8* %lsr.iv to <4 x i8>*
+ %lsr.iv1416 = bitcast i8* %lsr.iv14 to <4 x i8>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv13, i32 1, <4 x i1> %8, <4 x i8> undef)
+ %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
+ %wide.masked.load12 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv1416, i32 1, <4 x i1> %8, <4 x i8> undef)
+ %11 = zext <4 x i8> %wide.masked.load12 to <4 x i32>
+ %12 = mul nuw nsw <4 x i32> %11, %10
+ %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
+ %14 = add <4 x i32> %vec.phi, %13
+ %scevgep = getelementptr i8, i8* %lsr.iv, i32 4
+ %scevgep15 = getelementptr i8, i8* %lsr.iv14, i32 4
+ %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %16 = icmp ne i32 %15, 0
+ br i1 %16, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ define dso_local arm_aapcs_vfpcc i32 @add_var_i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
+ entry:
+ %cmp10.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv15 = phi i8* [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %15, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv14 = bitcast i8* %lsr.iv to <4 x i8>*
+ %lsr.iv1517 = bitcast i8* %lsr.iv15 to <4 x i8>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv14, i32 1, <4 x i1> %8, <4 x i8> undef)
+ %10 = zext <4 x i8> %wide.masked.load to <4 x i32>
+ %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv1517, i32 1, <4 x i1> %8, <4 x i8> undef)
+ %11 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
+ %12 = add <4 x i32> %vec.phi, %10
+ %13 = add <4 x i32> %12, %11
+ %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
+ %scevgep = getelementptr i8, i8* %lsr.iv, i32 4
+ %scevgep16 = getelementptr i8, i8* %lsr.iv15, i32 4
+ %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %16 = icmp ne i32 %15, 0
+ br i1 %16, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ define dso_local arm_aapcs_vfpcc i32 @mul_var_i16(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) {
+ entry:
+ %cmp9.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv14 = phi i16* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %15, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv13 = bitcast i16* %lsr.iv to <4 x i16>*
+ %lsr.iv1416 = bitcast i16* %lsr.iv14 to <4 x i16>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv13, i32 2, <4 x i1> %8, <4 x i16> undef)
+ %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
+ %wide.masked.load12 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1416, i32 2, <4 x i1> %8, <4 x i16> undef)
+ %11 = sext <4 x i16> %wide.masked.load12 to <4 x i32>
+ %12 = mul nsw <4 x i32> %11, %10
+ %13 = select <4 x i1> %8, <4 x i32> %12, <4 x i32> zeroinitializer
+ %14 = add <4 x i32> %vec.phi, %13
+ %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
+ %scevgep15 = getelementptr i16, i16* %lsr.iv14, i32 4
+ %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %16 = icmp ne i32 %15, 0
+ br i1 %16, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ define dso_local arm_aapcs_vfpcc i32 @add_var_i16(i16* nocapture readonly %a, i16* nocapture readonly %b, i32 %N) {
+ entry:
+ %cmp10.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp10.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv15 = phi i16* [ %scevgep16, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %14, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %15, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv14 = bitcast i16* %lsr.iv to <4 x i16>*
+ %lsr.iv1517 = bitcast i16* %lsr.iv15 to <4 x i16>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv14, i32 2, <4 x i1> %8, <4 x i16> undef)
+ %10 = sext <4 x i16> %wide.masked.load to <4 x i32>
+ %wide.masked.load13 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1517, i32 2, <4 x i1> %8, <4 x i16> undef)
+ %11 = sext <4 x i16> %wide.masked.load13 to <4 x i32>
+ %12 = add <4 x i32> %vec.phi, %10
+ %13 = add <4 x i32> %12, %11
+ %14 = select <4 x i1> %8, <4 x i32> %13, <4 x i32> %vec.phi
+ %scevgep = getelementptr i16, i16* %lsr.iv, i32 4
+ %scevgep16 = getelementptr i16, i16* %lsr.iv15, i32 4
+ %15 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %16 = icmp ne i32 %15, 0
+ br i1 %16, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %17 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %14)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %17, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ ; Function Attrs: norecurse nounwind readonly
+ define dso_local arm_aapcs_vfpcc i32 @mul_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
+ entry:
+ %cmp8.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv13 = phi i32* [ %scevgep14, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %13, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv12 = bitcast i32* %lsr.iv to <4 x i32>*
+ %lsr.iv1315 = bitcast i32* %lsr.iv13 to <4 x i32>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)
+ %wide.masked.load11 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1315, i32 4, <4 x i1> %8, <4 x i32> undef)
+ %10 = mul nsw <4 x i32> %wide.masked.load11, %wide.masked.load
+ %11 = select <4 x i1> %8, <4 x i32> %10, <4 x i32> zeroinitializer
+ %12 = add <4 x i32> %vec.phi, %11
+ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
+ %scevgep14 = getelementptr i32, i32* %lsr.iv13, i32 4
+ %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %14 = icmp ne i32 %13, 0
+ br i1 %14, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %15 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %12)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ ; Function Attrs: norecurse nounwind readonly
+ define dso_local arm_aapcs_vfpcc i32 @add_var_i32(i32* nocapture readonly %a, i32* nocapture readonly %b, i32 %N) local_unnamed_addr #0 {
+ entry:
+ %cmp9.not = icmp eq i32 %N, 0
+ %0 = add i32 %N, 3
+ %1 = lshr i32 %0, 2
+ %2 = shl nuw i32 %1, 2
+ %3 = add i32 %2, -4
+ %4 = lshr i32 %3, 2
+ %5 = add nuw nsw i32 %4, 1
+ br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph
+
+ vector.ph: ; preds = %entry
+ call void @llvm.set.loop.iterations.i32(i32 %5)
+ br label %vector.body
+
+ vector.body: ; preds = %vector.body, %vector.ph
+ %lsr.iv14 = phi i32* [ %scevgep15, %vector.body ], [ %b, %vector.ph ]
+ %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+ %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
+ %6 = phi i32 [ %5, %vector.ph ], [ %13, %vector.body ]
+ %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
+ %lsr.iv13 = bitcast i32* %lsr.iv to <4 x i32>*
+ %lsr.iv1416 = bitcast i32* %lsr.iv14 to <4 x i32>*
+ %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
+ %9 = sub i32 %7, 4
+ %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv13, i32 4, <4 x i1> %8, <4 x i32> undef)
+ %wide.masked.load12 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1416, i32 4, <4 x i1> %8, <4 x i32> undef)
+ %10 = add <4 x i32> %wide.masked.load, %vec.phi
+ %11 = add <4 x i32> %10, %wide.masked.load12
+ %12 = select <4 x i1> %8, <4 x i32> %11, <4 x i32> %vec.phi
+ %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
+ %scevgep15 = getelementptr i32, i32* %lsr.iv14, i32 4
+ %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %6, i32 1)
+ %14 = icmp ne i32 %13, 0
+ br i1 %14, label %vector.body, label %middle.block
+
+ middle.block: ; preds = %vector.body
+ %15 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %12)
+ br label %for.cond.cleanup
+
+ for.cond.cleanup: ; preds = %middle.block, %entry
+ %res.0.lcssa = phi i32 [ 0, %entry ], [ %15, %middle.block ]
+ ret i32 %res.0.lcssa
+ }
+
+ declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>)
+ declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
+ declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
+ declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
+ declare void @llvm.set.loop.iterations.i32(i32)
+ declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
+ declare <4 x i1> @llvm.arm.mve.vctp32(i32)
+
+...
+---
+name: mul_var_i8
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: mul_var_i8
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load 4 from %ir.lsr.iv13, align 1)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load 4 from %ir.lsr.iv1416, align 1)
+ ; CHECK: renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv13, align 1)
+ renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv1416, align 1)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = nuw nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
+---
+name: add_var_i8
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: add_var_i8
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 0, $noreg :: (load 4 from %ir.lsr.iv14, align 1)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load 4 from %ir.lsr.iv1517, align 1)
+ ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRBU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv14, align 1)
+ renamable $r1, renamable $q2 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv1517, align 1)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
+---
+name: mul_var_i16
+alignment: 2
+exposesReturnsTwice: false
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: mul_var_i16
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv13, align 2)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1416, align 2)
+ ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv13, align 2)
+ renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1416, align 2)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
+---
+name: add_var_i16
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: add_var_i16
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv14, align 2)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.lsr.iv1517, align 2)
+ ; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv14, align 2)
+ renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1517, align 2)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
+---
+name: mul_var_i32
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: mul_var_i32
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.lsr.iv12, align 4)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1315, align 4)
+ ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv12, align 4)
+ renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1315, align 4)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
+---
+name: add_var_i32
+alignment: 2
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: add_var_i32
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
+ ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ ; CHECK: t2IT 0, 4, implicit-def $itstate
+ ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+ ; CHECK: bb.1.vector.ph:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
+ ; CHECK: bb.2.vector.body (align 4):
+ ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0, $r1
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4)
+ ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4)
+ ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
+ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 0, killed $noreg, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
+ ; CHECK: bb.3.middle.block:
+ ; CHECK: liveins: $q0
+ ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ t2IT 0, 4, implicit-def $itstate
+ renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
+ tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
+
+ bb.1.vector.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $lr
+
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_register $r7
+ renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
+ renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
+ renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
+ renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+ t2DoLoopStart renamable $lr
+
+ bb.2.vector.body (align 4):
+ successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
+ MVE_VPST 4, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4)
+ renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4)
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
+ renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
+ tB %bb.3, 14 /* CC::al */, $noreg
+
+ bb.3.middle.block:
+ liveins: $q0
+
+ renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
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