[PATCH] D86613: [ARM][LowOverheadLoops] Liveouts and reductions

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp:643
+    return !isVectorPredicated(Def) &&
+           Def->getOpcode() == ARM::MVE_VMOVimmi32 &&
+           Def->getOperand(1).getImm() == 0;
----------------
SjoerdMeijer wrote:
> samparker wrote:
> > SjoerdMeijer wrote:
> > > Is this the only instruction that could zero initialise that def?
> > It's the only way that I saw, but there's probably more. It's the common and easy case to catch though.
> ah, because how we use `IsZeroInit`, we are on the safe side here, right? I missed that earlier.
> Not sure, perhaps XOR-ing the same register is the other common case? 
I don't think that's something I've seen, I guess that a move immediate is the obvious pattern to match in isel.


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  https://reviews.llvm.org/D86613/new/

https://reviews.llvm.org/D86613