[llvm] 5ba4d03 - [RISC-V] fmv.s/fmv.d should be as cheap as a move

[Alex Richardson via llvm-commits]

Author: Alex Richardson
Date: 2020-08-27T10:32:23+01:00
New Revision: 5ba4d0365b36de440d82b4672ccd41a5a7dd4592

URL: https://github.com/llvm/llvm-project/commit/5ba4d0365b36de440d82b4672ccd41a5a7dd4592
DIFF: https://github.com/llvm/llvm-project/commit/5ba4d0365b36de440d82b4672ccd41a5a7dd4592.diff

LOG: [RISC-V] fmv.s/fmv.d should be as cheap as a move

Since the canonical floatig-point move is fsgnj rd, rs, rs, we should
handle this case in RISCVInstrInfo::isAsCheapAsAMove().

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D86518

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1973a3bc538b..249264d1945f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -515,6 +515,11 @@ bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
   switch (Opcode) {
   default:
     break;
+  case RISCV::FSGNJ_D:
+  case RISCV::FSGNJ_S:
+    // The canonical floatig-point move is fsgnj rd, rs, rs.
+    return MI.getOperand(1).isReg() && MI.getOperand(2).isReg() &&
+           MI.getOperand(1).getReg() == MI.getOperand(2).getReg();
   case RISCV::ADDI:
   case RISCV::ORI:
   case RISCV::XORI: