[PATCH] D86681: [PowerPC] Fix the incorrect handling on scheduling heuristic

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: jsji, qiucf, PowerPC.
Herald added subscribers: shchenz, asbirlea, javed.absar, kbarton, hiraditya, nemanjai, MatzeB.
Herald added a project: LLVM.
steven.zhang requested review of this revision.

We didn't handle the scheduling heuristic for PowerPC well which might hit assertion when scheduler verifying is enabled. The semantics of tryCandidate(Cand, TryCand) is as follows:

- If the reason for TryCand is not NoCand, we will select TryCand. Otherwise, we will still select the Cand.

Current implementation is messy up with this semantics.

We need to handle two cases:

1. We want to schedule TryCand before Cand If the TryCand is not selected by base heuristic, select it only when the heuristic for Cand is NodeOrder. (Our heuristic has high priority than NodeOrder)
2. We want to schedule Cand before TryCand If the TryCand has been selected by base heuristic, select the Cand only when the heuristic for TryCand is NodeOrder.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86681

Files:
  llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
  llvm/test/CodeGen/PowerPC/botheightreduce.mir
  llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
  llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
  llvm/test/CodeGen/PowerPC/sched-addi.ll
  llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
  llvm/test/CodeGen/PowerPC/sms-phi-1.ll
  llvm/test/CodeGen/PowerPC/sms-simple.ll
  llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

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