[llvm] a60d10a - [NFC][Test] Update the test with utils/update_llc_test_checks.py
QingShan Zhang via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 22:03:11 PDT 2020
Author: QingShan Zhang
Date: 2020-08-27T05:02:55Z
New Revision: a60d10ac0a96756bb56970123196cd8ad117b70f
URL: https://github.com/llvm/llvm-project/commit/a60d10ac0a96756bb56970123196cd8ad117b70f
DIFF: https://github.com/llvm/llvm-project/commit/a60d10ac0a96756bb56970123196cd8ad117b70f.diff
LOG: [NFC][Test] Update the test with utils/update_llc_test_checks.py
Added:
Modified:
llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
index 12c9dfec5055..4d339e2383b3 100644
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
; test_no_prep:
@@ -19,8 +20,21 @@
define i64 @test_no_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_no_prep:
-; CHECK: addi r3, r3, 4004
-; CHECK: .LBB0_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: beq cr0, .LBB0_4
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r5, 1
+; CHECK-NEXT: addi r3, r3, 4004
+; CHECK-NEXT: li r6, -3
+; CHECK-NEXT: li r7, -2
+; CHECK-NEXT: li r8, -1
+; CHECK-NEXT: iselgt r5, r4, r5
+; CHECK-NEXT: mtctr r5
+; CHECK-NEXT: li r5, 0
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ldx r9, r3, r6
; CHECK-NEXT: ldx r10, r3, r7
; CHECK-NEXT: ldx r11, r3, r8
@@ -30,6 +44,12 @@ define i64 @test_no_prep(i8* %0, i32 signext %1) {
; CHECK-NEXT: mulld r9, r9, r11
; CHECK-NEXT: maddld r5, r9, r12, r5
; CHECK-NEXT: bdnz .LBB0_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: add r3, r5, r4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB0_4:
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %27, label %5
@@ -83,8 +103,19 @@ define i64 @test_no_prep(i8* %0, i32 signext %1) {
define i64 @test_ds_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_prep:
-; CHECK: addi r6, r3, 4002
-; CHECK: .LBB1_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: beq cr0, .LBB1_4
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r5, 1
+; CHECK-NEXT: addi r6, r3, 4002
+; CHECK-NEXT: li r7, -1
+; CHECK-NEXT: iselgt r3, r4, r5
+; CHECK-NEXT: mtctr r3
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ldx r9, r6, r7
; CHECK-NEXT: ld r10, 0(r6)
; CHECK-NEXT: ldx r11, r6, r5
@@ -95,6 +126,12 @@ define i64 @test_ds_prep(i8* %0, i32 signext %1) {
; CHECK-NEXT: maddld r3, r9, r6, r3
; CHECK-NEXT: mr r6, r8
; CHECK-NEXT: bdnz .LBB1_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB1_4:
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %27, label %5
@@ -158,8 +195,28 @@ define i64 @test_ds_prep(i8* %0, i32 signext %1) {
define i64 @test_max_number_reminder(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_max_number_reminder:
-; CHECK: addi r9, r3, 4002
-; CHECK: .LBB2_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT: beq cr0, .LBB2_3
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r5, 1
+; CHECK-NEXT: addi r9, r3, 4002
+; CHECK-NEXT: li r6, -1
+; CHECK-NEXT: li r7, 3
+; CHECK-NEXT: li r8, 5
+; CHECK-NEXT: li r10, 9
+; CHECK-NEXT: iselgt r3, r4, r5
+; CHECK-NEXT: mtctr r3
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: ldx r12, r9, r6
; CHECK-NEXT: ld r0, 0(r9)
; CHECK-NEXT: ldx r30, r9, r5
@@ -180,6 +237,18 @@ define i64 @test_max_number_reminder(i8* %0, i32 signext %1) {
; CHECK-NEXT: maddld r3, r12, r9, r3
; CHECK-NEXT: mr r9, r11
; CHECK-NEXT: bdnz .LBB2_2
+; CHECK-NEXT: b .LBB2_4
+; CHECK-NEXT: .LBB2_3:
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: .LBB2_4:
+; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %47, label %5
@@ -253,8 +322,19 @@ define i64 @test_max_number_reminder(i8* %0, i32 signext %1) {
define dso_local i64 @test_update_ds_prep_interact(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_update_ds_prep_interact:
-; CHECK: addi r3, r3, 3998
-; CHECK: .LBB3_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: beq cr0, .LBB3_4
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r6, 1
+; CHECK-NEXT: addi r3, r3, 3998
+; CHECK-NEXT: li r7, -1
+; CHECK-NEXT: iselgt r5, r4, r6
+; CHECK-NEXT: mtctr r5
+; CHECK-NEXT: li r5, 0
+; CHECK-NEXT: .p2align 5
+; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: ldu r8, 4(r3)
; CHECK-NEXT: ldx r9, r3, r7
; CHECK-NEXT: ldx r10, r3, r6
@@ -263,6 +343,12 @@ define dso_local i64 @test_update_ds_prep_interact(i8* %0, i32 signext %1) {
; CHECK-NEXT: mulld r8, r8, r10
; CHECK-NEXT: maddld r5, r8, r11, r5
; CHECK-NEXT: bdnz .LBB3_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: add r3, r5, r4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB3_4:
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %28, label %5
@@ -317,9 +403,20 @@ define dso_local i64 @test_update_ds_prep_interact(i8* %0, i32 signext %1) {
define i64 @test_update_ds_prep_nointeract(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_update_ds_prep_nointeract:
-; CHECK: addi r5, r3, 4000
-; CHECK: addi r3, r3, 4003
-; CHECK: .LBB4_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: beq cr0, .LBB4_4
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r6, 1
+; CHECK-NEXT: addi r5, r3, 4000
+; CHECK-NEXT: addi r3, r3, 4003
+; CHECK-NEXT: li r7, -1
+; CHECK-NEXT: iselgt r6, r4, r6
+; CHECK-NEXT: mtctr r6
+; CHECK-NEXT: li r6, 0
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: lbzu r8, 1(r5)
; CHECK-NEXT: ldx r9, r3, r7
; CHECK-NEXT: ld r10, 0(r3)
@@ -329,6 +426,12 @@ define i64 @test_update_ds_prep_nointeract(i8* %0, i32 signext %1) {
; CHECK-NEXT: mulld r8, r8, r10
; CHECK-NEXT: maddld r6, r8, r11, r6
; CHECK-NEXT: bdnz .LBB4_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: add r3, r6, r4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB4_4:
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %27, label %5
@@ -386,9 +489,21 @@ define i64 @test_update_ds_prep_nointeract(i8* %0, i32 signext %1) {
define dso_local i64 @test_ds_multiple_chains(i8* %0, i8* %1, i32 signext %2) {
; CHECK-LABEL: test_ds_multiple_chains:
-; CHECK: addi r3, r3, 4001
-; CHECK: addi r4, r4, 4001
-; CHECK: .LBB5_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r5, 0
+; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT: beq cr0, .LBB5_3
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: cmpldi r5, 1
+; CHECK-NEXT: li r6, 1
+; CHECK-NEXT: addi r3, r3, 4001
+; CHECK-NEXT: addi r4, r4, 4001
+; CHECK-NEXT: li r7, 9
+; CHECK-NEXT: iselgt r6, r5, r6
+; CHECK-NEXT: mtctr r6
+; CHECK-NEXT: li r6, 0
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: ld r8, 0(r3)
; CHECK-NEXT: ldx r9, r3, r7
; CHECK-NEXT: ld r10, 4(r3)
@@ -407,6 +522,13 @@ define dso_local i64 @test_ds_multiple_chains(i8* %0, i8* %1, i32 signext %2) {
; CHECK-NEXT: mulld r8, r8, r30
; CHECK-NEXT: maddld r6, r8, r9, r6
; CHECK-NEXT: bdnz .LBB5_2
+; CHECK-NEXT: b .LBB5_4
+; CHECK-NEXT: .LBB5_3:
+; CHECK-NEXT: li r6, 0
+; CHECK-NEXT: .LBB5_4:
+; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT: add r3, r6, r5
+; CHECK-NEXT: blr
%4 = sext i32 %2 to i64
%5 = icmp eq i32 %2, 0
br i1 %5, label %45, label %6
@@ -493,13 +615,43 @@ define dso_local i64 @test_ds_multiple_chains(i8* %0, i8* %1, i32 signext %2) {
define i64 @test_ds_cross_basic_blocks(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_cross_basic_blocks:
-; CHECK: addi r6, r3, 4009
-; CHECK: .LBB6_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplwi r4, 0
+; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT: beq cr0, .LBB6_8
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: cmpldi r4, 1
+; CHECK-NEXT: li r7, 1
+; CHECK-NEXT: addi r6, r3, 4009
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: iselgt r8, r4, r7
+; CHECK-NEXT: lis r4, -21846
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r9, -7
+; CHECK-NEXT: li r10, -6
+; CHECK-NEXT: li r11, 1
+; CHECK-NEXT: li r12, 1
+; CHECK-NEXT: li r30, 1
+; CHECK-NEXT: ld r5, 0(r5)
+; CHECK-NEXT: mtctr r8
+; CHECK-NEXT: li r8, -9
+; CHECK-NEXT: addi r5, r5, -1
+; CHECK-NEXT: ori r4, r4, 43691
+; CHECK-NEXT: li r29, 1
+; CHECK-NEXT: li r28, 1
+; CHECK-NEXT: b .LBB6_4
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: ldx r0, r6, r8
; CHECK-NEXT: add r28, r0, r28
; CHECK-NEXT: ld r0, -8(r6)
; CHECK-NEXT: add r29, r0, r29
-; CHECK-NEXT: .LBB6_3: #
+; CHECK-NEXT: .LBB6_3:
; CHECK-NEXT: addi r6, r6, 1
; CHECK-NEXT: mulld r0, r29, r28
; CHECK-NEXT: mulld r0, r0, r30
@@ -507,7 +659,7 @@ define i64 @test_ds_cross_basic_blocks(i8* %0, i32 signext %1) {
; CHECK-NEXT: mulld r0, r0, r11
; CHECK-NEXT: maddld r3, r0, r7, r3
; CHECK-NEXT: bdz .LBB6_9
-; CHECK-NEXT: .LBB6_4: #
+; CHECK-NEXT: .LBB6_4:
; CHECK-NEXT: lbzu r0, 1(r5)
; CHECK-NEXT: mulhwu r27, r0, r4
; CHECK-NEXT: rlwinm r26, r27, 0, 0, 30
@@ -516,22 +668,32 @@ define i64 @test_ds_cross_basic_blocks(i8* %0, i32 signext %1) {
; CHECK-NEXT: sub r0, r0, r27
; CHECK-NEXT: cmplwi r0, 1
; CHECK-NEXT: beq cr0, .LBB6_2
-; CHECK-NEXT: # %bb.5: #
+; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: clrlwi r0, r0, 24
; CHECK-NEXT: cmplwi r0, 2
; CHECK-NEXT: bne cr0, .LBB6_7
-; CHECK-NEXT: # %bb.6: #
+; CHECK-NEXT: # %bb.6:
; CHECK-NEXT: ldx r0, r6, r9
; CHECK-NEXT: add r30, r0, r30
; CHECK-NEXT: ld r0, -4(r6)
; CHECK-NEXT: add r12, r0, r12
; CHECK-NEXT: b .LBB6_3
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB6_7: #
+; CHECK-NEXT: .LBB6_7:
; CHECK-NEXT: ldx r0, r6, r10
; CHECK-NEXT: add r11, r0, r11
; CHECK-NEXT: ld r0, 0(r6)
; CHECK-NEXT: add r7, r0, r7
+; CHECK-NEXT: b .LBB6_3
+; CHECK-NEXT: .LBB6_8:
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: .LBB6_9:
+; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
+; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp eq i32 %1, 0
br i1 %4, label %66, label %5
@@ -636,8 +798,17 @@ define i64 @test_ds_cross_basic_blocks(i8* %0, i32 signext %1) {
define float @test_ds_float(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_float:
-; CHECK: addi r3, r3, 4002
-; CHECK: .LBB7_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpwi r4, 1
+; CHECK-NEXT: blt cr0, .LBB7_4
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: addi r3, r3, 4002
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: xxlxor f1, f1, f1
+; CHECK-NEXT: mtctr r4
+; CHECK-NEXT: li r4, -1
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: lfs f2, 0(r3)
; CHECK-NEXT: xsmulsp f0, f0, f2
@@ -648,6 +819,11 @@ define float @test_ds_float(i8* %0, i32 signext %1) {
; CHECK-NEXT: xsmulsp f0, f0, f4
; CHECK-NEXT: xsaddsp f1, f1, f0
; CHECK-NEXT: bdnz .LBB7_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB7_4:
+; CHECK-NEXT: xxlxor f1, f1, f1
+; CHECK-NEXT: blr
%3 = icmp sgt i32 %1, 0
br i1 %3, label %4, label %28
@@ -704,8 +880,17 @@ define float @test_ds_float(i8* %0, i32 signext %1) {
define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_combine_float_int:
-; CHECK: addi r3, r3, 4002
-; CHECK: .LBB8_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpwi r4, 1
+; CHECK-NEXT: blt cr0, .LBB8_4
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: addi r3, r3, 4002
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: xxlxor f1, f1, f1
+; CHECK-NEXT: mtctr r4
+; CHECK-NEXT: li r4, -1
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: lfd f4, 0(r3)
; CHECK-NEXT: lfsx f0, r3, r4
; CHECK-NEXT: xscvuxdsp f4, f4
@@ -717,6 +902,11 @@ define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
; CHECK-NEXT: xsmulsp f0, f3, f0
; CHECK-NEXT: xsaddsp f1, f1, f0
; CHECK-NEXT: bdnz .LBB8_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB8_4:
+; CHECK-NEXT: xxlxor f1, f1, f1
+; CHECK-NEXT: blr
%3 = icmp sgt i32 %1, 0
br i1 %3, label %4, label %29
@@ -773,9 +963,16 @@ define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
; CHECK-LABEL: test_ds_lwa_prep:
-; CHECK: addi r5, r3, 2
-; CHECK: li r6, -1
-; CHECK: .LBB9_2: #
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmpwi r4, 1
+; CHECK-NEXT: blt cr0, .LBB9_4
+; CHECK-NEXT: # %bb.1: # %.preheader
+; CHECK-NEXT: mtctr r4
+; CHECK-NEXT: addi r5, r3, 2
+; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: li r6, -1
+; CHECK-NEXT: .p2align 4
+; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: lwax r7, r5, r6
; CHECK-NEXT: lwa r8, 0(r5)
; CHECK-NEXT: lwa r9, 4(r5)
@@ -785,6 +982,12 @@ define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
; CHECK-NEXT: mulld r7, r7, r9
; CHECK-NEXT: maddld r3, r7, r10, r3
; CHECK-NEXT: bdnz .LBB9_2
+; CHECK-NEXT: # %bb.3:
+; CHECK-NEXT: add r3, r3, r4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB9_4:
+; CHECK-NEXT: addi r3, r4, 0
+; CHECK-NEXT: blr
%3 = sext i32 %1 to i64
%4 = icmp sgt i32 %1, 0
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