[PATCH] D86510: [compiler-rt] Fix atomic support functions on 32-bit architectures

[Alexander Richardson via Phabricator via llvm-commits]

arichardson added a comment.

In D86510#2240580 <https://reviews.llvm.org/D86510#2240580>, @efriedma wrote:

> In D86510#2240363 <https://reviews.llvm.org/D86510#2240363>, @dim wrote:
>
>> In D86510#2240266 <https://reviews.llvm.org/D86510#2240266>, @efriedma wrote:
>>
>>>> We are triggering -Watomic-alignment because `__c11_atomic_is_lock_free(8)` expands to a `__atomic_is_lock_free` call for mips32 since the property is not known statically, so the branch inside the switch emitted and contains a call to __atomic_load_8 which triggers the warning.
>>>
>>> Which -Watomic-alignment warning are we talking about?  The "max lock-free size" one, or the "actual alignment" one?
>>
>> The `warning: misaligned atomic operation may incur significant performance penalty` one.
>
> I can't seem to reproduce that... but it would indicate a bug in the code unrelated to the call to __atomic_is_lock_free.  atomic.c shouldn't be trying to use misaligned lock-free atomics.

See https://godbolt.org/z/h91ob3. This happens because the alignment of `void* src` is unknown and MIPS only supports aligned atomics.


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