[PATCH] D86665: [GlobalISel][IRTranslator] Generate better conditional branch lowering.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, arsenm, foad.
aemerson added a project: LLVM.
Herald added subscribers: atanasyan, jrtc27, hiraditya, rovka, sdardis.
aemerson requested review of this revision.
Herald added a subscriber: wdng.

This is a port of the functionality from SelectionDAG, which tries to find a tree of conditions from compares that are then combined using OR or AND, before using that result as the input to a branch. Instead of naively lowering the code as is, this change converts that into a sequence of conditional branches on the sub-expressions of the tree.

Like SelectionDAG, we re-use the case block codegen functionality from the switch lowering utils, which causes us to generate some different code. The result of which I've tried to mitigate in earlier combine patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86665

Files:
  llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
  llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll

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