[PATCH] D86510: [compiler-rt] Fix atomic support functions on 32-bit architectures

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> We are triggering -Watomic-alignment because `__c11_atomic_is_lock_free(8)` expands to a `__atomic_is_lock_free` call for mips32 since the property is not known statically, so the branch inside the switch emitted and contains a call to __atomic_load_8 which triggers the warning.

Which -Watomic-alignment warning are we talking about?  The "max lock-free size" one, or the "actual alignment" one?

> Therefore, this approach should be safe? And the optimization that checks the alignment and uses the atomic instructions instead of locks in the aligned case could be added later?

The way the code with this patch checks for "lock-free" assumes the pointer argument is aligned the same way an a pointer to a uintN_t would be.  That isn't correct in general.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D86510/new/

https://reviews.llvm.org/D86510