[PATCH] D86634: [AMDGPU] SILowerControlFlow::optimizeEndCF should remove empty basic block

[Alexander via Phabricator via llvm-commits]

alex-t created this revision.
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optimizeEndCF removes EXEC restoring instruction case this instruction is the only one except the branch to the single successor and that successor contains EXEC mask restoring instruction that was lowered from END_CF belonging to IF_ELSE. 
As a result of such optimization we get the basic block with the only one instruction that is a branch to the single successor.
In case the control flow can reach such an empty block from S_CBRANCH_EXEZ/EXECNZ it might happen that spill/reload instructions that were inserted later by register allocator are placed under exec == 0 condition and never execute.
Removing empty block solves the problem.

This change require further work to re-implement LIS updates. Recently, LIS is always nullptr in this pass. To enable it we need another patch to fix many places across the codegen.


https://reviews.llvm.org/D86634

Files:
  llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
  llvm/test/CodeGen/AMDGPU/collapse-endcf.mir


Index: llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
+++ llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
@@ -387,14 +387,12 @@
   ; GCN:   $exec = S_MOV_B64_term killed [[S_AND_B64_]]
   ; GCN:   S_CBRANCH_EXECZ %bb.4, implicit $exec
   ; GCN: bb.1:
-  ; GCN:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; GCN:   successors: %bb.2(0x40000000), %bb.5(0x40000000)
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
-  ; GCN:   S_CBRANCH_EXECZ %bb.3, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.5, implicit $exec
   ; GCN: bb.2:
-  ; GCN:   successors: %bb.3(0x80000000)
-  ; GCN: bb.3:
   ; GCN:   successors: %bb.5(0x80000000)
   ; GCN:   S_BRANCH %bb.5
   ; GCN: bb.4:
Index: llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -156,7 +156,6 @@
     AU.addPreservedID(LiveVariablesID);
     AU.addPreservedID(MachineLoopInfoID);
     AU.addPreservedID(MachineDominatorsID);
-    AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 };
@@ -615,6 +614,38 @@
       if (LIS)
         LIS->RemoveMachineInstrFromMaps(*MI);
       MI->eraseFromParent();
+      if (MBB.size() == 1 && MBB.begin()->getOpcode() == AMDGPU::S_BRANCH) {
+        MachineBasicBlock *Succ = MBB.begin()->getOperand(0).getMBB();
+        SmallVector<MachineBasicBlock *, 2> Preds;
+        for (auto &Pred : MBB.predecessors()) {
+          Preds.push_back(Pred);
+        }
+        for (auto P : Preds) {
+          P->removeSuccessor(&MBB);
+          P->addSuccessor(Succ);
+          MachineBasicBlock::iterator I(P->getFirstInstrTerminator());
+          while (I != P->end()) {
+            if (I->isBranch()) {
+              if (TII->getBranchDestBlock(*I) == &MBB) {
+                I->getOperand(0).setMBB(Succ);
+                break;
+              }
+            }
+            I++;
+          }
+          if (I == P->end()) {
+            MachineInstr *Br =
+                BuildMI(P, DebugLoc(), TII->get(AMDGPU::S_BRANCH)).addMBB(Succ);
+            if (LIS)
+              LIS->InsertMachineInstrInMaps(*Br);
+          }
+        }
+        MBB.removeSuccessor(Succ);
+        MBB.eraseFromParent();
+        if (LIS) {
+          LIS->RemoveMachineInstrFromMaps(*MBB.begin());
+        }
+      }
     }
   }
 }


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