[PATCH] D86449: [SelectionDAG] Handle non-power-of-2 bitwidths in expandROT

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6287
+    HsVal =
+        DAG.getNode(HsOpc, DL, VT, DAG.getNode(HsOpc, DL, VT, Op0, One), HsAmt);
+  }
----------------
spatel wrote:
> This can't be right - both shifts are `HsOpc`. We need another test with a variable shift amount to make sure this is correct?
It's correct. We want to shift by 1..32, so we do a shift by 1 and then a shift by 0..31.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86449/new/

https://reviews.llvm.org/D86449