[llvm] c485343 - [PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation

[Nemanja Ivanovic via llvm-commits]

Author: Nemanja Ivanovic
Date: 2020-08-24T16:22:59-05:00
New Revision: c485343c8310086ff7ee4aaf40330b4c4b35e99f

URL: https://github.com/llvm/llvm-project/commit/c485343c8310086ff7ee4aaf40330b4c4b35e99f
DIFF: https://github.com/llvm/llvm-project/commit/c485343c8310086ff7ee4aaf40330b4c4b35e99f.diff

LOG: [PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation

We initially missed the subtract-immediate in this transformation.
This patch just adds that.

Differential revision: https://reviews.llvm.org/D84659

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/test/CodeGen/PowerPC/pr44183.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 5c59e0f7b2af..0732e0f0ace3 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3760,6 +3760,20 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
     }
     return false;
   }
+  case PPC::SUBFIC:
+  case PPC::SUBFIC8: {
+    // Only transform this if the CARRY implicit operand is dead.
+    if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
+      return false;
+    int64_t Minuend = MI.getOperand(2).getImm();
+    if (isInt<16>(Minuend - SExtImm)) {
+      ReplaceWithLI = true;
+      Is64BitLI = Opc == PPC::SUBFIC8;
+      NewImm = Minuend - SExtImm;
+      break;
+    }
+    return false;
+  }
   case PPC::RLDICL:
   case PPC::RLDICL_rec:
   case PPC::RLDICL_32:

diff  --git a/llvm/test/CodeGen/PowerPC/pr44183.ll b/llvm/test/CodeGen/PowerPC/pr44183.ll
index a2cf40521f55..c639d47cdffb 100644
--- a/llvm/test/CodeGen/PowerPC/pr44183.ll
+++ b/llvm/test/CodeGen/PowerPC/pr44183.ll
@@ -8,37 +8,33 @@ define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind al
 ; CHECK-LABEL: _ZN1m1nEv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
-; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
-; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    mr r30, r3
-; CHECK-NEXT:    li r3, 4
 ; CHECK-NEXT:    ld r4, 16(r30)
 ; CHECK-NEXT:    ld r5, 8(r30)
-; CHECK-NEXT:    subfic r29, r3, 64
-; CHECK-NEXT:    rldicl r3, r5, 60, 4
-; CHECK-NEXT:    sld r4, r4, r29
-; CHECK-NEXT:    lwz r5, 36(r30)
-; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    rlwinm r3, r3, 31, 0, 0
-; CHECK-NEXT:    clrlwi r4, r5, 31
+; CHECK-NEXT:    lwz r6, 36(r30)
+; CHECK-NEXT:    rldicl r5, r5, 60, 4
+; CHECK-NEXT:    sldi r4, r4, 60
+; CHECK-NEXT:    or r4, r4, r5
+; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
+; CHECK-NEXT:    clrlwi r4, r6, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld r3, 16(r30)
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-NEXT:    sld r3, r3, r29
+; CHECK-NEXT:    sldi r3, r3, 60
 ; CHECK-NEXT:    or r3, r3, r4
 ; CHECK-NEXT:    sldi r3, r3, 31
 ; CHECK-NEXT:    clrldi r4, r3, 32
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi r1, r1, 64
+; CHECK-NEXT:    addi r1, r1, 48
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 entry: