[PATCH] D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 287294.
HsiangKai added a comment.

Add VRNoV0 register class.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84732/new/

https://reviews.llvm.org/D84732

Files:
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/MC/RISCV/rvv/compare.s
  llvm/test/MC/RISCV/rvv/invalid.s

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