[llvm] 41ba9d7 - [PowerPC] Support constrained vector fp/int conversion
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 19:19:44 PDT 2020
Author: Qiu Chaofan
Date: 2020-08-24T10:10:27+08:00
New Revision: 41ba9d77231eac32f8a022eedffd261c47020dd4
URL: https://github.com/llvm/llvm-project/commit/41ba9d77231eac32f8a022eedffd261c47020dd4
DIFF: https://github.com/llvm/llvm-project/commit/41ba9d77231eac32f8a022eedffd261c47020dd4.diff
LOG: [PowerPC] Support constrained vector fp/int conversion
This patch makes these operations legal, and add necessary codegen
patterns.
There's still some issue similar to D77033 for conversion from v1i128
type. But normal type tests synced in vector-constrained-fp-intrinsic
are passed successfully.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D83654
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index e19b47532587..18e04ff6f516 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -824,6 +824,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SELECT, MVT::v4i32,
Subtarget.useCRBits() ? Legal : Expand);
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
+ setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
+ setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
@@ -1002,6 +1006,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
+ setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
+ setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
@@ -1010,6 +1018,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// Custom handling for partial vectors of integers converted to
// floating point. We already have optimal handling for v2i32 through
// the DAG combine, so those aren't necessary.
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
+ setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
+ setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
@@ -8346,17 +8362,19 @@ static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) {
SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
const SDLoc &dl) const {
-
+ bool IsStrict = Op->isStrictFPOpcode();
unsigned Opc = Op.getOpcode();
- assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP) &&
+ SDValue Src = Op.getOperand(IsStrict ? 1 : 0);
+ assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP ||
+ Opc == ISD::STRICT_UINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP) &&
"Unexpected conversion type");
assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) &&
"Supports conversions to v2f64/v4f32 only.");
- bool SignedConv = Opc == ISD::SINT_TO_FP;
+ bool SignedConv = Opc == ISD::SINT_TO_FP || Opc == ISD::STRICT_SINT_TO_FP;
bool FourEltRes = Op.getValueType() == MVT::v4f32;
- SDValue Wide = widenVec(DAG, Op.getOperand(0), dl);
+ SDValue Wide = widenVec(DAG, Src, dl);
EVT WideVT = Wide.getValueType();
unsigned WideNumElts = WideVT.getVectorNumElements();
MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64;
@@ -8381,7 +8399,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
SDValue Extend;
if (SignedConv) {
Arrange = DAG.getBitcast(IntermediateVT, Arrange);
- EVT ExtVT = Op.getOperand(0).getValueType();
+ EVT ExtVT = Src.getValueType();
if (Subtarget.hasP9Altivec())
ExtVT = EVT::getVectorVT(*DAG.getContext(), WideVT.getVectorElementType(),
IntermediateVT.getVectorNumElements());
@@ -8391,6 +8409,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
} else
Extend = DAG.getNode(ISD::BITCAST, dl, IntermediateVT, Arrange);
+ if (IsStrict)
+ return DAG.getNode(Opc, dl, {Op.getValueType(), MVT::Other},
+ {Op.getOperand(0), Extend});
+
return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
}
@@ -10648,6 +10670,28 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
}
}
+void PPCTargetLowering::LowerOperationWrapper(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const {
+ SDValue Res = LowerOperation(SDValue(N, 0), DAG);
+
+ if (!Res.getNode())
+ return;
+
+ // Take the return value as-is if original node has only one result.
+ if (N->getNumValues() == 1) {
+ Results.push_back(Res);
+ return;
+ }
+
+ // New node should have the same number of results.
+ assert((N->getNumValues() == Res->getNumValues()) &&
+ "Lowering returned the wrong number of results!");
+
+ for (unsigned i = 0; i < N->getNumValues(); ++i)
+ Results.push_back(Res.getValue(i));
+}
+
void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const {
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index ec76363955b1..8ee243017e7f 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -753,6 +753,12 @@ namespace llvm {
///
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+ /// LowerOperationWrapper - Place custom new result values for node in
+ /// Results.
+ void LowerOperationWrapper(SDNode *N,
+ SmallVectorImpl<SDValue> &Results,
+ SelectionDAG &DAG) const override;
+
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index f9f9fb02fa6d..c3ee1c7ea18a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -821,7 +821,7 @@ let hasSideEffects = 0 in {
def XVCVDPSXDS : XX2Form<60, 472,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpsxds $XT, $XB", IIC_VecFP,
- [(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
+ [(set v2i64:$XT, (any_fp_to_sint v2f64:$XB))]>;
def XVCVDPSXWS : XX2Form<60, 216,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpsxws $XT, $XB", IIC_VecFP,
@@ -829,7 +829,7 @@ let hasSideEffects = 0 in {
def XVCVDPUXDS : XX2Form<60, 456,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpuxds $XT, $XB", IIC_VecFP,
- [(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
+ [(set v2i64:$XT, (any_fp_to_uint v2f64:$XB))]>;
def XVCVDPUXWS : XX2Form<60, 200,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvdpuxws $XT, $XB", IIC_VecFP,
@@ -845,18 +845,18 @@ let hasSideEffects = 0 in {
def XVCVSPSXWS : XX2Form<60, 152,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvspsxws $XT, $XB", IIC_VecFP,
- [(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
+ [(set v4i32:$XT, (any_fp_to_sint v4f32:$XB))]>;
def XVCVSPUXDS : XX2Form<60, 392,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvspuxds $XT, $XB", IIC_VecFP, []>;
def XVCVSPUXWS : XX2Form<60, 136,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvspuxws $XT, $XB", IIC_VecFP,
- [(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
+ [(set v4i32:$XT, (any_fp_to_uint v4f32:$XB))]>;
def XVCVSXDDP : XX2Form<60, 504,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvsxddp $XT, $XB", IIC_VecFP,
- [(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
+ [(set v2f64:$XT, (any_sint_to_fp v2i64:$XB))]>;
def XVCVSXDSP : XX2Form<60, 440,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvsxdsp $XT, $XB", IIC_VecFP,
@@ -868,11 +868,11 @@ let hasSideEffects = 0 in {
def XVCVSXWSP : XX2Form<60, 184,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvsxwsp $XT, $XB", IIC_VecFP,
- [(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
+ [(set v4f32:$XT, (any_sint_to_fp v4i32:$XB))]>;
def XVCVUXDDP : XX2Form<60, 488,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvuxddp $XT, $XB", IIC_VecFP,
- [(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
+ [(set v2f64:$XT, (any_uint_to_fp v2i64:$XB))]>;
def XVCVUXDSP : XX2Form<60, 424,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvuxdsp $XT, $XB", IIC_VecFP,
@@ -884,7 +884,7 @@ let hasSideEffects = 0 in {
def XVCVUXWSP : XX2Form<60, 168,
(outs vsrc:$XT), (ins vsrc:$XB),
"xvcvuxwsp $XT, $XB", IIC_VecFP,
- [(set v4f32:$XT, (uint_to_fp v4i32:$XB))]>;
+ [(set v4f32:$XT, (any_uint_to_fp v4i32:$XB))]>;
// Rounding Instructions respecting current rounding mode
def XSRDPIC : XX2Form<60, 107,
diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
index cefa662c0eae..1acf71e8f159 100644
--- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
@@ -5653,800 +5653,3143 @@ entry:
ret <4 x double> %min
}
-define <1 x float> @constrained_vector_fptrunc_v1f64() #0 {
-; PC64LE-LABEL: constrained_vector_fptrunc_v1f64:
+define <1 x i32> @constrained_vector_fptosi_v1i32_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI95_0 at toc@ha
-; PC64LE-NEXT: lfd 0, .LCPI95_0 at toc@l(3)
-; PC64LE-NEXT: xsrsp 1, 0
+; PC64LE-NEXT: lfs 0, .LCPI95_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: mffprwz 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI95_0 at toc@ha
-; PC64LE9-NEXT: lfd 0, .LCPI95_0 at toc@l(3)
-; PC64LE9-NEXT: xsrsp 1, 0
+; PC64LE9-NEXT: lfs 0, .LCPI95_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: blr
entry:
- %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
- <1 x double><double 42.1>,
- metadata !"round.dynamic",
- metadata !"fpexcept.strict") #1
- ret <1 x float> %result
+ %result = call <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f32(
+ <1 x float><float 42.0>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i32> %result
}
-define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
-; PC64LE-LABEL: constrained_vector_fptrunc_v2f64:
+define <2 x i32> @constrained_vector_fptosi_v2i32_v2f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI96_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI96_1 at toc@ha
-; PC64LE-NEXT: lfd 0, .LCPI96_0 at toc@l(3)
-; PC64LE-NEXT: lfd 1, .LCPI96_1 at toc@l(4)
-; PC64LE-NEXT: xsrsp 0, 0
-; PC64LE-NEXT: xsrsp 1, 1
-; PC64LE-NEXT: xscvdpspn 0, 0
-; PC64LE-NEXT: xscvdpspn 1, 1
-; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
-; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: lfs 0, .LCPI96_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI96_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: xscvdpsxws 1, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: mtvsrwz 35, 4
; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fptrunc_v2f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI96_0 at toc@ha
-; PC64LE9-NEXT: lfd 0, .LCPI96_0 at toc@l(3)
+; PC64LE9-NEXT: lfs 0, .LCPI96_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI96_1 at toc@ha
-; PC64LE9-NEXT: xsrsp 0, 0
-; PC64LE9-NEXT: xscvdpspn 0, 0
-; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
-; PC64LE9-NEXT: lfd 0, .LCPI96_1 at toc@l(3)
-; PC64LE9-NEXT: xsrsp 0, 0
-; PC64LE9-NEXT: xscvdpspn 0, 0
-; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: lfs 0, .LCPI96_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: blr
entry:
- %result = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
- <2 x double><double 42.1, double 42.2>,
- metadata !"round.dynamic",
- metadata !"fpexcept.strict") #1
- ret <2 x float> %result
+ %result = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f32(
+ <2 x float><float 42.0, float 43.0>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i32> %result
}
-define <3 x float> @constrained_vector_fptrunc_v3f64() #0 {
-; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
+define <3 x i32> @constrained_vector_fptosi_v3i32_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI97_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI97_1 at toc@ha
-; PC64LE-NEXT: lfd 0, .LCPI97_0 at toc@l(3)
-; PC64LE-NEXT: lfd 1, .LCPI97_1 at toc@l(4)
+; PC64LE-NEXT: lfs 0, .LCPI97_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI97_1 at toc@l(4)
; PC64LE-NEXT: addis 3, 2, .LCPI97_3 at toc@ha
-; PC64LE-NEXT: xsrsp 0, 0
-; PC64LE-NEXT: lfd 2, .LCPI97_3 at toc@l(3)
+; PC64LE-NEXT: lfs 2, .LCPI97_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: xscvdpsxws 1, 1
+; PC64LE-NEXT: xscvdpsxws 2, 2
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
; PC64LE-NEXT: addis 3, 2, .LCPI97_2 at toc@ha
-; PC64LE-NEXT: xsrsp 1, 1
+; PC64LE-NEXT: mtvsrwz 35, 4
; PC64LE-NEXT: addi 3, 3, .LCPI97_2 at toc@l
-; PC64LE-NEXT: xsrsp 2, 2
-; PC64LE-NEXT: xscvdpspn 0, 0
-; PC64LE-NEXT: xscvdpspn 1, 1
-; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
-; PC64LE-NEXT: xscvdpspn 0, 2
-; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: mffprwz 4, 2
; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: lvx 3, 0, 3
-; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: mtvsrwz 36, 4
; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI97_0 at toc@ha
-; PC64LE9-NEXT: lfd 0, .LCPI97_0 at toc@l(3)
+; PC64LE9-NEXT: lfs 0, .LCPI97_0 at toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI97_1 at toc@ha
-; PC64LE9-NEXT: xsrsp 0, 0
-; PC64LE9-NEXT: xscvdpspn 0, 0
-; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
-; PC64LE9-NEXT: lfd 0, .LCPI97_1 at toc@l(3)
+; PC64LE9-NEXT: lfs 1, .LCPI97_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: xscvdpsxws 0, 1
+; PC64LE9-NEXT: mtvsrws 34, 3
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI97_2 at toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI97_2 at toc@l
-; PC64LE9-NEXT: xsrsp 0, 0
-; PC64LE9-NEXT: xscvdpspn 0, 0
-; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI97_3 at toc@ha
-; PC64LE9-NEXT: lfd 0, .LCPI97_3 at toc@l(3)
-; PC64LE9-NEXT: xsrsp 0, 0
-; PC64LE9-NEXT: xscvdpspn 0, 0
-; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: lfs 0, .LCPI97_3 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 36, 3
; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr
entry:
- %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
- <3 x double><double 42.1, double 42.2,
- double 42.3>,
- metadata !"round.dynamic",
- metadata !"fpexcept.strict") #1
- ret <3 x float> %result
+ %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32(
+ <3 x float><float 42.0, float 43.0,
+ float 44.0>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i32> %result
}
-define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
-; PC64LE-LABEL: constrained_vector_fptrunc_v4f64:
+define <4 x i32> @constrained_vector_fptosi_v4i32_v4f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI98_0 at toc@ha
-; PC64LE-NEXT: addis 4, 2, .LCPI98_1 at toc@ha
-; PC64LE-NEXT: addis 5, 2, .LCPI98_2 at toc@ha
-; PC64LE-NEXT: addis 6, 2, .LCPI98_3 at toc@ha
-; PC64LE-NEXT: lfd 0, .LCPI98_0 at toc@l(3)
-; PC64LE-NEXT: lfd 1, .LCPI98_1 at toc@l(4)
-; PC64LE-NEXT: lfd 2, .LCPI98_2 at toc@l(5)
-; PC64LE-NEXT: lfd 3, .LCPI98_3 at toc@l(6)
-; PC64LE-NEXT: xxmrghd 0, 1, 0
-; PC64LE-NEXT: xxmrghd 1, 3, 2
-; PC64LE-NEXT: xvcvdpsp 34, 0
-; PC64LE-NEXT: xvcvdpsp 35, 1
-; PC64LE-NEXT: vmrgew 2, 3, 2
+; PC64LE-NEXT: addi 3, 3, .LCPI98_0 at toc@l
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xvcvspsxws 34, 34
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI98_0 at toc@ha
-; PC64LE9-NEXT: lfd 0, .LCPI98_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI98_1 at toc@ha
-; PC64LE9-NEXT: lfd 1, .LCPI98_1 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI98_2 at toc@ha
-; PC64LE9-NEXT: xxmrghd 0, 1, 0
-; PC64LE9-NEXT: xvcvdpsp 34, 0
-; PC64LE9-NEXT: lfd 0, .LCPI98_2 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI98_3 at toc@ha
-; PC64LE9-NEXT: lfd 1, .LCPI98_3 at toc@l(3)
-; PC64LE9-NEXT: xxmrghd 0, 1, 0
-; PC64LE9-NEXT: xvcvdpsp 35, 0
-; PC64LE9-NEXT: vmrgew 2, 3, 2
+; PC64LE9-NEXT: addi 3, 3, .LCPI98_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: xvcvspsxws 34, 0
; PC64LE9-NEXT: blr
entry:
- %result = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
- <4 x double><double 42.1, double 42.2,
- double 42.3, double 42.4>,
- metadata !"round.dynamic",
- metadata !"fpexcept.strict") #1
- ret <4 x float> %result
+ %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(
+ <4 x float><float 42.0, float 43.0,
+ float 44.0, float 45.0>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i32> %result
}
-define <1 x double> @constrained_vector_fpext_v1f32() #0 {
-; PC64LE-LABEL: constrained_vector_fpext_v1f32:
+define <1 x i64> @constrained_vector_fptosi_v1i64_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI99_0 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI99_0 at toc@l(3)
+; PC64LE-NEXT: lfs 0, .LCPI99_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fpext_v1f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI99_0 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI99_0 at toc@l(3)
+; PC64LE9-NEXT: lfs 0, .LCPI99_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
; PC64LE9-NEXT: blr
entry:
- %result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(
- <1 x float><float 42.0>,
- metadata !"fpexcept.strict") #1
- ret <1 x double> %result
+ %result = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f32(
+ <1 x float><float 42.0>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i64> %result
}
-define <2 x double> @constrained_vector_fpext_v2f32() #0 {
-; PC64LE-LABEL: constrained_vector_fpext_v2f32:
+define <2 x i64> @constrained_vector_fptosi_v2i64_v2f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI100_1 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI100_0 at toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI100_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: xscvdpsxds 1, 1
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 1, 4
; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fpext_v2f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI100_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI100_1 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI100_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI100_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI100_1 at toc@l(3)
-; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI100_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 34, 4, 3
; PC64LE9-NEXT: blr
entry:
- %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
+ %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(
<2 x float><float 42.0, float 43.0>,
- metadata !"fpexcept.strict") #1
- ret <2 x double> %result
+ metadata !"fpexcept.strict") #0
+ ret <2 x i64> %result
}
-define <3 x double> @constrained_vector_fpext_v3f32() #0 {
-; PC64LE-LABEL: constrained_vector_fpext_v3f32:
+define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI101_1 at toc@ha
; PC64LE-NEXT: addis 5, 2, .LCPI101_2 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI101_0 at toc@l(3)
-; PC64LE-NEXT: lfs 2, .LCPI101_1 at toc@l(4)
-; PC64LE-NEXT: lfs 3, .LCPI101_2 at toc@l(5)
+; PC64LE-NEXT: lfs 0, .LCPI101_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI101_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI101_2 at toc@l(5)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: xscvdpsxds 1, 1
+; PC64LE-NEXT: xscvdpsxds 2, 2
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI101_0 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI101_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI101_1 at toc@ha
-; PC64LE9-NEXT: lfs 2, .LCPI101_1 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI101_2 at toc@ha
-; PC64LE9-NEXT: lfs 3, .LCPI101_2 at toc@l(3)
+; PC64LE9-NEXT: addis 4, 2, .LCPI101_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI101_2 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI101_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI101_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: lfs 0, .LCPI101_2 at toc@l(5)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 5, 0
; PC64LE9-NEXT: blr
entry:
- %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
+ %result = call <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f32(
<3 x float><float 42.0, float 43.0,
float 44.0>,
- metadata !"fpexcept.strict") #1
- ret <3 x double> %result
+ metadata !"fpexcept.strict") #0
+ ret <3 x i64> %result
}
-define <4 x double> @constrained_vector_fpext_v4f32() #0 {
-; PC64LE-LABEL: constrained_vector_fpext_v4f32:
+define <4 x i64> @constrained_vector_fptosi_v4i64_v4f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI102_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI102_1 at toc@ha
-; PC64LE-NEXT: addis 5, 2, .LCPI102_2 at toc@ha
-; PC64LE-NEXT: addis 6, 2, .LCPI102_3 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI102_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI102_2 at toc@ha
; PC64LE-NEXT: lfs 1, .LCPI102_1 at toc@l(4)
-; PC64LE-NEXT: lfs 2, .LCPI102_2 at toc@l(5)
-; PC64LE-NEXT: lfs 3, .LCPI102_3 at toc@l(6)
+; PC64LE-NEXT: addis 4, 2, .LCPI102_3 at toc@ha
+; PC64LE-NEXT: lfs 2, .LCPI102_2 at toc@l(3)
+; PC64LE-NEXT: lfs 3, .LCPI102_3 at toc@l(4)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: xscvdpsxds 1, 1
+; PC64LE-NEXT: xscvdpsxds 2, 2
+; PC64LE-NEXT: xscvdpsxds 3, 3
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mffprd 3, 2
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: mffprd 4, 3
+; PC64LE-NEXT: mtfprd 2, 3
; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: mtfprd 3, 4
; PC64LE-NEXT: xxmrghd 35, 3, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_fpext_v4f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI102_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI102_1 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI102_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI102_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI102_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI102_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 34, 4, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI102_2 at toc@ha
-; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: addis 4, 2, .LCPI102_3 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI102_2 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI102_3 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI102_3 at toc@l(3)
-; PC64LE9-NEXT: xxmrghd 35, 1, 0
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI102_3 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 35, 4, 3
; PC64LE9-NEXT: blr
entry:
- %result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
+ %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f32(
<4 x float><float 42.0, float 43.0,
float 44.0, float 45.0>,
- metadata !"fpexcept.strict") #1
- ret <4 x double> %result
+ metadata !"fpexcept.strict") #0
+ ret <4 x i64> %result
}
-define <1 x float> @constrained_vector_ceil_v1f32() #0 {
-; PC64LE-LABEL: constrained_vector_ceil_v1f32:
+define <1 x i32> @constrained_vector_fptosi_v1i32_v1f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v1i32_v1f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI103_0 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI103_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI103_1 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI103_1 at toc@l(3)
-; PC64LE-NEXT: xsrdpip 0, 0
+; PC64LE-NEXT: lfd 0, .LCPI103_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: mffprwz 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v1i32_v1f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI103_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI103_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI103_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI103_1 at toc@l(3)
-; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: lfd 0, .LCPI103_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: blr
entry:
- %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
- <1 x float> <float 1.5>,
- metadata !"fpexcept.strict") #1
- ret <1 x float> %ceil
+ %result = call <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f64(
+ <1 x double><double 42.1>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i32> %result
}
-define <2 x double> @constrained_vector_ceil_v2f64() #0 {
-; PC64LE-LABEL: constrained_vector_ceil_v2f64:
+
+define <2 x i32> @constrained_vector_fptosi_v2i32_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v2i32_v2f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI104_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI104_1 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI104_0 at toc@l
-; PC64LE-NEXT: lxvd2x 0, 0, 3
-; PC64LE-NEXT: addi 3, 4, .LCPI104_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: xvrdpip 0, 0
-; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: lfd 0, .LCPI104_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI104_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: xscvdpsxws 1, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_ceil_v2f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v2i32_v2f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI104_0 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI104_0 at toc@l
-; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: lfd 0, .LCPI104_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI104_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI104_1 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xvrdpip 0, 0
+; PC64LE9-NEXT: lfd 0, .LCPI104_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
+; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: blr
entry:
- %ceil = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
- <2 x double> <double 1.1, double 1.9>,
- metadata !"fpexcept.strict") #1
- ret <2 x double> %ceil
+ %result = call <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(
+ <2 x double><double 42.1, double 42.2>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i32> %result
}
-define <3 x float> @constrained_vector_ceil_v3f32() #0 {
-; PC64LE-LABEL: constrained_vector_ceil_v3f32:
+define <3 x i32> @constrained_vector_fptosi_v3i32_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v3i32_v3f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI105_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI105_1 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI105_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI105_2 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI105_1 at toc@l(4)
-; PC64LE-NEXT: lfs 2, .LCPI105_2 at toc@l(3)
+; PC64LE-NEXT: lfd 0, .LCPI105_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI105_1 at toc@l(4)
; PC64LE-NEXT: addis 3, 2, .LCPI105_3 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI105_3 at toc@l
-; PC64LE-NEXT: xsrdpip 0, 0
-; PC64LE-NEXT: lvx 2, 0, 3
-; PC64LE-NEXT: xsrdpip 0, 1
-; PC64LE-NEXT: xsrdpip 0, 2
+; PC64LE-NEXT: lfd 2, .LCPI105_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: xscvdpsxws 1, 1
+; PC64LE-NEXT: xscvdpsxws 2, 2
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI105_2 at toc@ha
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: addi 3, 3, .LCPI105_2 at toc@l
+; PC64LE-NEXT: mffprwz 4, 2
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: mtvsrwz 36, 4
+; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_ceil_v3f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI105_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI105_0 at toc@l(3)
+; PC64LE9-NEXT: lfd 0, .LCPI105_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI105_1 at toc@ha
-; PC64LE9-NEXT: xsrdpip 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI105_1 at toc@l(3)
+; PC64LE9-NEXT: lfd 0, .LCPI105_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI105_2 at toc@ha
-; PC64LE9-NEXT: xsrdpip 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI105_2 at toc@l(3)
+; PC64LE9-NEXT: addi 3, 3, .LCPI105_2 at toc@l
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI105_3 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI105_3 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: lfd 0, .LCPI105_3 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 36, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr
entry:
- %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
- <3 x float> <float 1.5, float 2.5, float 3.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x float> %ceil
+ %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(
+ <3 x double><double 42.1, double 42.2,
+ double 42.3>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i32> %result
}
-define <3 x double> @constrained_vector_ceil_v3f64() #0 {
-; PC64LE-LABEL: constrained_vector_ceil_v3f64:
+define <4 x i32> @constrained_vector_fptosi_v4i32_v4f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v4i32_v4f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI106_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI106_1 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI106_0 at toc@l(3)
-; PC64LE-NEXT: addi 3, 4, .LCPI106_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: addis 3, 2, .LCPI106_2 at toc@ha
-; PC64LE-NEXT: xsrdpip 0, 0
-; PC64LE-NEXT: xvrdpip 0, 1
-; PC64LE-NEXT: lfs 1, .LCPI106_2 at toc@l(3)
-; PC64LE-NEXT: fmr 2, 1
-; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: addis 5, 2, .LCPI106_2 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI106_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI106_3 at toc@ha
+; PC64LE-NEXT: lfd 1, .LCPI106_1 at toc@l(4)
+; PC64LE-NEXT: lfd 2, .LCPI106_2 at toc@l(5)
+; PC64LE-NEXT: lfd 3, .LCPI106_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxws 0, 0
+; PC64LE-NEXT: xscvdpsxws 1, 1
+; PC64LE-NEXT: xscvdpsxws 2, 2
+; PC64LE-NEXT: xscvdpsxws 3, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mffprwz 5, 2
+; PC64LE-NEXT: mffprwz 6, 3
+; PC64LE-NEXT: rldimi 4, 3, 32, 0
+; PC64LE-NEXT: mtfprd 0, 4
+; PC64LE-NEXT: rldimi 6, 5, 32, 0
+; PC64LE-NEXT: mtfprd 1, 6
+; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_ceil_v3f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v4i32_v4f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI106_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI106_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI106_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI106_1 at toc@l
-; PC64LE9-NEXT: xsrdpip 0, 0
-; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 4, 2, .LCPI106_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI106_3 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI106_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI106_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 4, 0
+; PC64LE9-NEXT: rldimi 4, 3, 32, 0
; PC64LE9-NEXT: addis 3, 2, .LCPI106_2 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI106_2 at toc@l(3)
-; PC64LE9-NEXT: xvrdpip 0, 0
-; PC64LE9-NEXT: fmr 2, 1
-; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: lfd 0, .LCPI106_2 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI106_3 at toc@l(5)
+; PC64LE9-NEXT: xscvdpsxws 0, 0
+; PC64LE9-NEXT: mffprwz 5, 0
+; PC64LE9-NEXT: rldimi 5, 3, 32, 0
+; PC64LE9-NEXT: mtvsrdd 34, 5, 4
; PC64LE9-NEXT: blr
entry:
- %ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64(
- <3 x double> <double 1.1, double 1.9, double 1.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x double> %ceil
+ %result = call <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f64(
+ <4 x double><double 42.1, double 42.2,
+ double 42.3, double 42.4>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i32> %result
}
-define <1 x float> @constrained_vector_floor_v1f32() #0 {
-; PC64LE-LABEL: constrained_vector_floor_v1f32:
+define <1 x i64> @constrained_vector_fptosi_v1i64_v1f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v1i64_v1f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI107_0 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI107_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI107_1 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI107_1 at toc@l(3)
-; PC64LE-NEXT: xsrdpim 0, 0
+; PC64LE-NEXT: lfd 0, .LCPI107_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_floor_v1f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v1i64_v1f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI107_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI107_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI107_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI107_1 at toc@l(3)
-; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: lfd 0, .LCPI107_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
; PC64LE9-NEXT: blr
entry:
- %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
- <1 x float> <float 1.5>,
- metadata !"fpexcept.strict") #1
- ret <1 x float> %floor
+ %result = call <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f64(
+ <1 x double><double 42.1>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i64> %result
}
-
-define <2 x double> @constrained_vector_floor_v2f64() #0 {
-; PC64LE-LABEL: constrained_vector_floor_v2f64:
+define <2 x i64> @constrained_vector_fptosi_v2i64_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI108_0 at toc@ha
-; PC64LE-NEXT: addis 4, 2, .LCPI108_1 at toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI108_0 at toc@l
; PC64LE-NEXT: lxvd2x 0, 0, 3
-; PC64LE-NEXT: addi 3, 4, .LCPI108_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: xvrdpim 0, 0
-; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: xxswapd 0, 0
+; PC64LE-NEXT: xvcvdpsxds 34, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_floor_v2f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v2i64_v2f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI108_0 at toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI108_0 at toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3
-; PC64LE9-NEXT: addis 3, 2, .LCPI108_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI108_1 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xvrdpim 0, 0
+; PC64LE9-NEXT: xvcvdpsxds 34, 0
; PC64LE9-NEXT: blr
entry:
- %floor = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
- <2 x double> <double 1.1, double 1.9>,
- metadata !"fpexcept.strict") #1
- ret <2 x double> %floor
+ %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(
+ <2 x double><double 42.1, double 42.2>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i64> %result
}
-define <3 x float> @constrained_vector_floor_v3f32() #0 {
-; PC64LE-LABEL: constrained_vector_floor_v3f32:
+define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v3i64_v3f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI109_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI109_1 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI109_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI109_2 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI109_1 at toc@l(4)
-; PC64LE-NEXT: lfs 2, .LCPI109_2 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI109_3 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI109_3 at toc@l
-; PC64LE-NEXT: xsrdpim 0, 0
-; PC64LE-NEXT: lvx 2, 0, 3
-; PC64LE-NEXT: xsrdpim 0, 1
-; PC64LE-NEXT: xsrdpim 0, 2
+; PC64LE-NEXT: addis 5, 2, .LCPI109_2 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI109_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI109_1 at toc@l(4)
+; PC64LE-NEXT: lfd 2, .LCPI109_2 at toc@l(5)
+; PC64LE-NEXT: xscvdpsxds 0, 0
+; PC64LE-NEXT: xscvdpsxds 1, 1
+; PC64LE-NEXT: xscvdpsxds 2, 2
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_floor_v3f32:
+; PC64LE9-LABEL: constrained_vector_fptosi_v3i64_v3f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI109_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI109_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI109_1 at toc@ha
-; PC64LE9-NEXT: xsrdpim 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI109_1 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI109_2 at toc@ha
-; PC64LE9-NEXT: xsrdpim 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI109_2 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI109_3 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI109_3 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: addis 4, 2, .LCPI109_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI109_2 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI109_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI109_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: lfd 0, .LCPI109_2 at toc@l(5)
+; PC64LE9-NEXT: xscvdpsxds 0, 0
+; PC64LE9-NEXT: mffprd 5, 0
; PC64LE9-NEXT: blr
entry:
- %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
- <3 x float> <float 1.5, float 2.5, float 3.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x float> %floor
+ %result = call <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f64(
+ <3 x double><double 42.1, double 42.2,
+ double 42.3>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i64> %result
}
-define <3 x double> @constrained_vector_floor_v3f64() #0 {
-; PC64LE-LABEL: constrained_vector_floor_v3f64:
+define <4 x i64> @constrained_vector_fptosi_v4i64_v4f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI110_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI110_1 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI110_0 at toc@l(3)
+; PC64LE-NEXT: addi 3, 3, .LCPI110_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
; PC64LE-NEXT: addi 3, 4, .LCPI110_1 at toc@l
; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: addis 3, 2, .LCPI110_2 at toc@ha
-; PC64LE-NEXT: xsrdpim 0, 0
-; PC64LE-NEXT: xvrdpim 0, 1
-; PC64LE-NEXT: lfs 1, .LCPI110_2 at toc@l(3)
-; PC64LE-NEXT: fmr 2, 1
-; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: xxswapd 0, 0
+; PC64LE-NEXT: xxswapd 1, 1
+; PC64LE-NEXT: xvcvdpsxds 35, 0
+; PC64LE-NEXT: xvcvdpsxds 34, 1
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_floor_v3f64:
+; PC64LE9-LABEL: constrained_vector_fptosi_v4i64_v4f64:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI110_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI110_0 at toc@l(3)
+; PC64LE9-NEXT: addi 3, 3, .LCPI110_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI110_1 at toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI110_1 at toc@l
-; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: xvcvdpsxds 35, 0
; PC64LE9-NEXT: lxvx 0, 0, 3
-; PC64LE9-NEXT: addis 3, 2, .LCPI110_2 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI110_2 at toc@l(3)
-; PC64LE9-NEXT: xvrdpim 0, 0
-; PC64LE9-NEXT: fmr 2, 1
-; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: xvcvdpsxds 34, 0
; PC64LE9-NEXT: blr
entry:
- %floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64(
- <3 x double> <double 1.1, double 1.9, double 1.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x double> %floor
+ %result = call <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f64(
+ <4 x double><double 42.1, double 42.2,
+ double 42.3, double 42.4>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i64> %result
}
-define <1 x float> @constrained_vector_round_v1f32() #0 {
-; PC64LE-LABEL: constrained_vector_round_v1f32:
+define <1 x i32> @constrained_vector_fptoui_v1i32_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI111_0 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI111_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI111_1 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI111_1 at toc@l(3)
-; PC64LE-NEXT: xsrdpi 0, 0
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: mffprwz 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_round_v1f32:
+; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI111_0 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI111_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI111_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI111_1 at toc@l(3)
-; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
; PC64LE9-NEXT: blr
entry:
- %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
- <1 x float> <float 1.5>,
- metadata !"fpexcept.strict") #1
- ret <1 x float> %round
+ %result = call <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f32(
+ <1 x float><float 42.0>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i32> %result
}
-define <2 x double> @constrained_vector_round_v2f64() #0 {
-; PC64LE-LABEL: constrained_vector_round_v2f64:
+define <2 x i32> @constrained_vector_fptoui_v2i32_v2f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI112_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI112_1 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI112_0 at toc@l
-; PC64LE-NEXT: lxvd2x 0, 0, 3
-; PC64LE-NEXT: addi 3, 4, .LCPI112_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: xvrdpi 0, 0
-; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: lfs 0, .LCPI112_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI112_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: xscvdpuxws 1, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: vmrghw 2, 3, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_round_v2f64:
+; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI112_0 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI112_0 at toc@l
-; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: lfs 0, .LCPI112_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI112_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI112_1 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xvrdpi 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI112_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
+; PC64LE9-NEXT: vmrghw 2, 3, 2
; PC64LE9-NEXT: blr
entry:
- %round = call <2 x double> @llvm.experimental.constrained.round.v2f64(
- <2 x double> <double 1.1, double 1.9>,
- metadata !"fpexcept.strict") #1
- ret <2 x double> %round
+ %result = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f32(
+ <2 x float><float 42.0, float 43.0>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i32> %result
}
-define <3 x float> @constrained_vector_round_v3f32() #0 {
-; PC64LE-LABEL: constrained_vector_round_v3f32:
+define <3 x i32> @constrained_vector_fptoui_v3i32_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI113_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI113_1 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI113_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI113_2 at toc@ha
; PC64LE-NEXT: lfs 1, .LCPI113_1 at toc@l(4)
-; PC64LE-NEXT: lfs 2, .LCPI113_2 at toc@l(3)
; PC64LE-NEXT: addis 3, 2, .LCPI113_3 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI113_3 at toc@l
-; PC64LE-NEXT: xsrdpi 0, 0
-; PC64LE-NEXT: lvx 2, 0, 3
-; PC64LE-NEXT: xsrdpi 0, 1
-; PC64LE-NEXT: xsrdpi 0, 2
+; PC64LE-NEXT: lfs 2, .LCPI113_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: xscvdpuxws 1, 1
+; PC64LE-NEXT: xscvdpuxws 2, 2
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI113_2 at toc@ha
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: addi 3, 3, .LCPI113_2 at toc@l
+; PC64LE-NEXT: mffprwz 4, 2
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: mtvsrwz 36, 4
+; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_round_v3f32:
+; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI113_0 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI113_0 at toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI113_1 at toc@ha
-; PC64LE9-NEXT: xsrdpi 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI113_1 at toc@l(3)
+; PC64LE9-NEXT: lfs 1, .LCPI113_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: xscvdpuxws 0, 1
+; PC64LE9-NEXT: mtvsrws 34, 3
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI113_2 at toc@ha
-; PC64LE9-NEXT: xsrdpi 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI113_2 at toc@l(3)
+; PC64LE9-NEXT: addi 3, 3, .LCPI113_2 at toc@l
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI113_3 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI113_3 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI113_3 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 36, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: blr
entry:
- %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
- <3 x float> <float 1.5, float 2.5, float 3.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x float> %round
+ %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32(
+ <3 x float><float 42.0, float 43.0,
+ float 44.0>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i32> %result
}
-
-define <3 x double> @constrained_vector_round_v3f64() #0 {
-; PC64LE-LABEL: constrained_vector_round_v3f64:
+define <4 x i32> @constrained_vector_fptoui_v4i32_v4f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f32:
; PC64LE: # %bb.0: # %entry
-; PC64LE-NEXT: addis 4, 2, .LCPI114_1 at toc@ha
; PC64LE-NEXT: addis 3, 2, .LCPI114_0 at toc@ha
-; PC64LE-NEXT: addi 4, 4, .LCPI114_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 4
-; PC64LE-NEXT: addis 4, 2, .LCPI114_3 at toc@ha
-; PC64LE-NEXT: lfs 0, .LCPI114_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI114_2 at toc@ha
-; PC64LE-NEXT: lfs 2, .LCPI114_3 at toc@l(4)
-; PC64LE-NEXT: xsrdpi 0, 0
-; PC64LE-NEXT: xvrdpi 0, 1
-; PC64LE-NEXT: lfs 1, .LCPI114_2 at toc@l(3)
-; PC64LE-NEXT: fmr 3, 2
+; PC64LE-NEXT: addi 3, 3, .LCPI114_0 at toc@l
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xvcvspuxws 34, 34
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_round_v3f64:
+; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI114_0 at toc@ha
-; PC64LE9-NEXT: lfs 0, .LCPI114_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI114_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI114_1 at toc@l
-; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: addi 3, 3, .LCPI114_0 at toc@l
; PC64LE9-NEXT: lxvx 0, 0, 3
-; PC64LE9-NEXT: addis 3, 2, .LCPI114_2 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI114_2 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI114_3 at toc@ha
-; PC64LE9-NEXT: lfs 2, .LCPI114_3 at toc@l(3)
-; PC64LE9-NEXT: xvrdpi 0, 0
-; PC64LE9-NEXT: fmr 3, 2
+; PC64LE9-NEXT: xvcvspuxws 34, 0
; PC64LE9-NEXT: blr
entry:
- %round = call <3 x double> @llvm.experimental.constrained.round.v3f64(
- <3 x double> <double 1.1, double 1.9, double 1.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x double> %round
+ %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(
+ <4 x float><float 42.0, float 43.0,
+ float 44.0, float 45.0>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i32> %result
}
-define <1 x float> @constrained_vector_trunc_v1f32() #0 {
-; PC64LE-LABEL: constrained_vector_trunc_v1f32:
+define <1 x i64> @constrained_vector_fptoui_v1i64_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI115_0 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI115_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI115_1 at toc@ha
-; PC64LE-NEXT: lfs 1, .LCPI115_1 at toc@l(3)
-; PC64LE-NEXT: xsrdpiz 0, 0
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: mffprd 3, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
+; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI115_0 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI115_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI115_1 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI115_1 at toc@l(3)
-; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
; PC64LE9-NEXT: blr
entry:
- %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
- <1 x float> <float 1.5>,
- metadata !"fpexcept.strict") #1
- ret <1 x float> %trunc
+ %result = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f32(
+ <1 x float><float 42.0>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i64> %result
}
-define <2 x double> @constrained_vector_trunc_v2f64() #0 {
-; PC64LE-LABEL: constrained_vector_trunc_v2f64:
+define <2 x i64> @constrained_vector_fptoui_v2i64_v2f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI116_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI116_1 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI116_0 at toc@l
-; PC64LE-NEXT: lxvd2x 0, 0, 3
-; PC64LE-NEXT: addi 3, 4, .LCPI116_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
-; PC64LE-NEXT: xvrdpiz 0, 0
-; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: lfs 0, .LCPI116_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI116_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: xscvdpuxds 1, 1
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_trunc_v2f64:
+; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI116_0 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI116_0 at toc@l
-; PC64LE9-NEXT: lxvx 0, 0, 3
-; PC64LE9-NEXT: addis 3, 2, .LCPI116_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI116_1 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xvrdpiz 0, 0
+; PC64LE9-NEXT: addis 4, 2, .LCPI116_1 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI116_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI116_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 34, 4, 3
; PC64LE9-NEXT: blr
entry:
- %trunc = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
- <2 x double> <double 1.1, double 1.9>,
- metadata !"fpexcept.strict") #1
- ret <2 x double> %trunc
+ %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(
+ <2 x float><float 42.0, float 43.0>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i64> %result
}
-define <3 x float> @constrained_vector_trunc_v3f32() #0 {
-; PC64LE-LABEL: constrained_vector_trunc_v3f32:
+define <3 x i64> @constrained_vector_fptoui_v3i64_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI117_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI117_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI117_2 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI117_0 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI117_2 at toc@ha
; PC64LE-NEXT: lfs 1, .LCPI117_1 at toc@l(4)
-; PC64LE-NEXT: lfs 2, .LCPI117_2 at toc@l(3)
-; PC64LE-NEXT: addis 3, 2, .LCPI117_3 at toc@ha
-; PC64LE-NEXT: addi 3, 3, .LCPI117_3 at toc@l
-; PC64LE-NEXT: xsrdpiz 0, 0
-; PC64LE-NEXT: lvx 2, 0, 3
-; PC64LE-NEXT: xsrdpiz 0, 1
-; PC64LE-NEXT: xsrdpiz 0, 2
+; PC64LE-NEXT: lfs 2, .LCPI117_2 at toc@l(5)
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: xscvdpuxds 1, 1
+; PC64LE-NEXT: xscvdpuxds 2, 2
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mffprd 5, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_trunc_v3f32:
+; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI117_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI117_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI117_2 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI117_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI117_1 at toc@ha
-; PC64LE9-NEXT: xsrdpiz 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI117_1 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI117_2 at toc@ha
-; PC64LE9-NEXT: xsrdpiz 0, 0
-; PC64LE9-NEXT: lfs 0, .LCPI117_2 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI117_3 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI117_3 at toc@l
-; PC64LE9-NEXT: lxvx 34, 0, 3
-; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI117_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: lfs 0, .LCPI117_2 at toc@l(5)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 5, 0
; PC64LE9-NEXT: blr
entry:
- %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
- <3 x float> <float 1.5, float 2.5, float 3.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x float> %trunc
+ %result = call <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f32(
+ <3 x float><float 42.0, float 43.0,
+ float 44.0>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i64> %result
}
-define <3 x double> @constrained_vector_trunc_v3f64() #0 {
-; PC64LE-LABEL: constrained_vector_trunc_v3f64:
+define <4 x i64> @constrained_vector_fptoui_v4i64_v4f32() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f32:
; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI118_0 at toc@ha
; PC64LE-NEXT: addis 4, 2, .LCPI118_1 at toc@ha
; PC64LE-NEXT: lfs 0, .LCPI118_0 at toc@l(3)
-; PC64LE-NEXT: addi 3, 4, .LCPI118_1 at toc@l
-; PC64LE-NEXT: lxvd2x 1, 0, 3
; PC64LE-NEXT: addis 3, 2, .LCPI118_2 at toc@ha
-; PC64LE-NEXT: xsrdpiz 0, 0
-; PC64LE-NEXT: xvrdpiz 0, 1
-; PC64LE-NEXT: lfs 1, .LCPI118_2 at toc@l(3)
-; PC64LE-NEXT: fmr 2, 1
-; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: lfs 1, .LCPI118_1 at toc@l(4)
+; PC64LE-NEXT: addis 4, 2, .LCPI118_3 at toc@ha
+; PC64LE-NEXT: lfs 2, .LCPI118_2 at toc@l(3)
+; PC64LE-NEXT: lfs 3, .LCPI118_3 at toc@l(4)
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: xscvdpuxds 1, 1
+; PC64LE-NEXT: xscvdpuxds 2, 2
+; PC64LE-NEXT: xscvdpuxds 3, 3
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mffprd 3, 2
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: mffprd 4, 3
+; PC64LE-NEXT: mtfprd 2, 3
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: mtfprd 3, 4
+; PC64LE-NEXT: xxmrghd 35, 3, 2
; PC64LE-NEXT: blr
;
-; PC64LE9-LABEL: constrained_vector_trunc_v3f64:
+; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f32:
; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI118_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI118_1 at toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI118_0 at toc@l(3)
-; PC64LE9-NEXT: addis 3, 2, .LCPI118_1 at toc@ha
-; PC64LE9-NEXT: addi 3, 3, .LCPI118_1 at toc@l
-; PC64LE9-NEXT: xsrdpiz 0, 0
-; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI118_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 34, 4, 3
; PC64LE9-NEXT: addis 3, 2, .LCPI118_2 at toc@ha
-; PC64LE9-NEXT: lfs 1, .LCPI118_2 at toc@l(3)
-; PC64LE9-NEXT: xvrdpiz 0, 0
-; PC64LE9-NEXT: fmr 2, 1
-; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: addis 4, 2, .LCPI118_3 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI118_2 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfs 0, .LCPI118_3 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: mtvsrdd 35, 4, 3
; PC64LE9-NEXT: blr
entry:
- %trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64(
- <3 x double> <double 1.1, double 1.9, double 1.5>,
- metadata !"fpexcept.strict") #1
- ret <3 x double> %trunc
+ %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f32(
+ <4 x float><float 42.0, float 43.0,
+ float 44.0, float 45.0>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i64> %result
+}
+
+define <1 x i32> @constrained_vector_fptoui_v1i32_v1f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v1i32_v1f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI119_0 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI119_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v1i32_v1f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI119_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI119_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f64(
+ <1 x double><double 42.1>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i32> %result
+}
+
+define <2 x i32> @constrained_vector_fptoui_v2i32_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v2i32_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI120_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI120_1 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI120_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI120_1 at toc@l(4)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: xscvdpuxws 1, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v2i32_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI120_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI120_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI120_1 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI120_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f64(
+ <2 x double><double 42.1, double 42.2>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i32> %result
+}
+
+define <3 x i32> @constrained_vector_fptoui_v3i32_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v3i32_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI121_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI121_1 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI121_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI121_1 at toc@l(4)
+; PC64LE-NEXT: addis 3, 2, .LCPI121_3 at toc@ha
+; PC64LE-NEXT: lfd 2, .LCPI121_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: xscvdpuxws 1, 1
+; PC64LE-NEXT: xscvdpuxws 2, 2
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtvsrwz 34, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI121_2 at toc@ha
+; PC64LE-NEXT: mtvsrwz 35, 4
+; PC64LE-NEXT: addi 3, 3, .LCPI121_2 at toc@l
+; PC64LE-NEXT: mffprwz 4, 2
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: mtvsrwz 36, 4
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI121_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI121_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 34, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI121_1 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI121_1 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 35, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI121_2 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI121_2 at toc@l
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI121_3 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI121_3 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: mtvsrws 36, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(
+ <3 x double><double 42.1, double 42.2,
+ double 42.3>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i32> %result
+}
+
+define <4 x i32> @constrained_vector_fptoui_v4i32_v4f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v4i32_v4f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI122_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI122_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI122_2 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI122_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI122_3 at toc@ha
+; PC64LE-NEXT: lfd 1, .LCPI122_1 at toc@l(4)
+; PC64LE-NEXT: lfd 2, .LCPI122_2 at toc@l(5)
+; PC64LE-NEXT: lfd 3, .LCPI122_3 at toc@l(3)
+; PC64LE-NEXT: xscvdpuxws 0, 0
+; PC64LE-NEXT: xscvdpuxws 1, 1
+; PC64LE-NEXT: xscvdpuxws 2, 2
+; PC64LE-NEXT: xscvdpuxws 3, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mffprwz 5, 2
+; PC64LE-NEXT: mffprwz 6, 3
+; PC64LE-NEXT: rldimi 4, 3, 32, 0
+; PC64LE-NEXT: mtfprd 0, 4
+; PC64LE-NEXT: rldimi 6, 5, 32, 0
+; PC64LE-NEXT: mtfprd 1, 6
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v4i32_v4f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI122_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI122_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI122_3 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI122_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI122_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 4, 0
+; PC64LE9-NEXT: rldimi 4, 3, 32, 0
+; PC64LE9-NEXT: addis 3, 2, .LCPI122_2 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI122_2 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI122_3 at toc@l(5)
+; PC64LE9-NEXT: xscvdpuxws 0, 0
+; PC64LE9-NEXT: mffprwz 5, 0
+; PC64LE9-NEXT: rldimi 5, 3, 32, 0
+; PC64LE9-NEXT: mtvsrdd 34, 5, 4
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f64(
+ <4 x double><double 42.1, double 42.2,
+ double 42.3, double 42.4>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i32> %result
+}
+
+define <1 x i64> @constrained_vector_fptoui_v1i64_v1f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v1i64_v1f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI123_0 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI123_0 at toc@l(3)
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v1i64_v1f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI123_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI123_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f64(
+ <1 x double><double 42.1>,
+ metadata !"fpexcept.strict") #0
+ ret <1 x i64> %result
+}
+
+define <2 x i64> @constrained_vector_fptoui_v2i64_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v2i64_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI124_0 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI124_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: xxswapd 0, 0
+; PC64LE-NEXT: xvcvdpuxds 34, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v2i64_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI124_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI124_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: xvcvdpuxds 34, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(
+ <2 x double><double 42.1, double 42.2>,
+ metadata !"fpexcept.strict") #0
+ ret <2 x i64> %result
+}
+
+define <3 x i64> @constrained_vector_fptoui_v3i64_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v3i64_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI125_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI125_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI125_2 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI125_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI125_1 at toc@l(4)
+; PC64LE-NEXT: lfd 2, .LCPI125_2 at toc@l(5)
+; PC64LE-NEXT: xscvdpuxds 0, 0
+; PC64LE-NEXT: xscvdpuxds 1, 1
+; PC64LE-NEXT: xscvdpuxds 2, 2
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mffprd 4, 1
+; PC64LE-NEXT: mffprd 5, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v3i64_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI125_0 at toc@ha
+; PC64LE9-NEXT: addis 4, 2, .LCPI125_1 at toc@ha
+; PC64LE9-NEXT: addis 5, 2, .LCPI125_2 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI125_0 at toc@l(3)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 3, 0
+; PC64LE9-NEXT: lfd 0, .LCPI125_1 at toc@l(4)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 4, 0
+; PC64LE9-NEXT: lfd 0, .LCPI125_2 at toc@l(5)
+; PC64LE9-NEXT: xscvdpuxds 0, 0
+; PC64LE9-NEXT: mffprd 5, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f64(
+ <3 x double><double 42.1, double 42.2,
+ double 42.3>,
+ metadata !"fpexcept.strict") #0
+ ret <3 x i64> %result
+}
+
+define <4 x i64> @constrained_vector_fptoui_v4i64_v4f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptoui_v4i64_v4f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI126_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI126_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI126_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: addi 3, 4, .LCPI126_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: xxswapd 0, 0
+; PC64LE-NEXT: xxswapd 1, 1
+; PC64LE-NEXT: xvcvdpuxds 35, 0
+; PC64LE-NEXT: xvcvdpuxds 34, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptoui_v4i64_v4f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI126_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI126_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI126_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI126_1 at toc@l
+; PC64LE9-NEXT: xvcvdpuxds 35, 0
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: xvcvdpuxds 34, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f64(
+ <4 x double><double 42.1, double 42.2,
+ double 42.3, double 42.4>,
+ metadata !"fpexcept.strict") #0
+ ret <4 x i64> %result
+}
+
+define <1 x float> @constrained_vector_fptrunc_v1f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptrunc_v1f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI127_0 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI127_0 at toc@l(3)
+; PC64LE-NEXT: xsrsp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI127_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI127_0 at toc@l(3)
+; PC64LE9-NEXT: xsrsp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
+ <1 x double><double 42.1>,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #1
+ ret <1 x float> %result
+}
+
+define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptrunc_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI128_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI128_1 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI128_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI128_1 at toc@l(4)
+; PC64LE-NEXT: xsrsp 0, 0
+; PC64LE-NEXT: xsrsp 1, 1
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptrunc_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI128_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI128_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI128_1 at toc@ha
+; PC64LE9-NEXT: xsrsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: lfd 0, .LCPI128_1 at toc@l(3)
+; PC64LE9-NEXT: xsrsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(
+ <2 x double><double 42.1, double 42.2>,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #1
+ ret <2 x float> %result
+}
+
+define <3 x float> @constrained_vector_fptrunc_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptrunc_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI129_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI129_1 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI129_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI129_1 at toc@l(4)
+; PC64LE-NEXT: addis 3, 2, .LCPI129_3 at toc@ha
+; PC64LE-NEXT: xsrsp 0, 0
+; PC64LE-NEXT: lfd 2, .LCPI129_3 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI129_2 at toc@ha
+; PC64LE-NEXT: xsrsp 1, 1
+; PC64LE-NEXT: addi 3, 3, .LCPI129_2 at toc@l
+; PC64LE-NEXT: xsrsp 2, 2
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xscvdpspn 0, 2
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI129_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI129_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI129_1 at toc@ha
+; PC64LE9-NEXT: xsrsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: lfd 0, .LCPI129_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI129_2 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI129_2 at toc@l
+; PC64LE9-NEXT: xsrsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI129_3 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI129_3 at toc@l(3)
+; PC64LE9-NEXT: xsrsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
+ <3 x double><double 42.1, double 42.2,
+ double 42.3>,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #1
+ ret <3 x float> %result
+}
+
+define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
+; PC64LE-LABEL: constrained_vector_fptrunc_v4f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI130_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI130_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI130_2 at toc@ha
+; PC64LE-NEXT: addis 6, 2, .LCPI130_3 at toc@ha
+; PC64LE-NEXT: lfd 0, .LCPI130_0 at toc@l(3)
+; PC64LE-NEXT: lfd 1, .LCPI130_1 at toc@l(4)
+; PC64LE-NEXT: lfd 2, .LCPI130_2 at toc@l(5)
+; PC64LE-NEXT: lfd 3, .LCPI130_3 at toc@l(6)
+; PC64LE-NEXT: xxmrghd 0, 1, 0
+; PC64LE-NEXT: xxmrghd 1, 3, 2
+; PC64LE-NEXT: xvcvdpsp 34, 0
+; PC64LE-NEXT: xvcvdpsp 35, 1
+; PC64LE-NEXT: vmrgew 2, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fptrunc_v4f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI130_0 at toc@ha
+; PC64LE9-NEXT: lfd 0, .LCPI130_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI130_1 at toc@ha
+; PC64LE9-NEXT: lfd 1, .LCPI130_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI130_2 at toc@ha
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 34, 0
+; PC64LE9-NEXT: lfd 0, .LCPI130_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI130_3 at toc@ha
+; PC64LE9-NEXT: lfd 1, .LCPI130_3 at toc@l(3)
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 35, 0
+; PC64LE9-NEXT: vmrgew 2, 3, 2
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(
+ <4 x double><double 42.1, double 42.2,
+ double 42.3, double 42.4>,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #1
+ ret <4 x float> %result
+}
+
+define <1 x double> @constrained_vector_fpext_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_fpext_v1f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI131_0 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI131_0 at toc@l(3)
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fpext_v1f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI131_0 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI131_0 at toc@l(3)
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(
+ <1 x float><float 42.0>,
+ metadata !"fpexcept.strict") #1
+ ret <1 x double> %result
+}
+
+define <2 x double> @constrained_vector_fpext_v2f32() #0 {
+; PC64LE-LABEL: constrained_vector_fpext_v2f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI132_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI132_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI132_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI132_1 at toc@l(4)
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fpext_v2f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI132_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI132_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI132_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI132_1 at toc@l(3)
+; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
+ <2 x float><float 42.0, float 43.0>,
+ metadata !"fpexcept.strict") #1
+ ret <2 x double> %result
+}
+
+define <3 x double> @constrained_vector_fpext_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_fpext_v3f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI133_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI133_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI133_2 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE-NEXT: lfs 2, .LCPI133_1 at toc@l(4)
+; PC64LE-NEXT: lfs 3, .LCPI133_2 at toc@l(5)
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI133_0 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI133_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI133_1 at toc@ha
+; PC64LE9-NEXT: lfs 2, .LCPI133_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI133_2 at toc@ha
+; PC64LE9-NEXT: lfs 3, .LCPI133_2 at toc@l(3)
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
+ <3 x float><float 42.0, float 43.0,
+ float 44.0>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x double> %result
+}
+
+define <4 x double> @constrained_vector_fpext_v4f32() #0 {
+; PC64LE-LABEL: constrained_vector_fpext_v4f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI134_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI134_1 at toc@ha
+; PC64LE-NEXT: addis 5, 2, .LCPI134_2 at toc@ha
+; PC64LE-NEXT: addis 6, 2, .LCPI134_3 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI134_0 at toc@l(3)
+; PC64LE-NEXT: lfs 1, .LCPI134_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI134_2 at toc@l(5)
+; PC64LE-NEXT: lfs 3, .LCPI134_3 at toc@l(6)
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: xxmrghd 35, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_fpext_v4f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI134_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI134_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI134_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI134_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI134_2 at toc@ha
+; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: lfs 0, .LCPI134_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI134_3 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI134_3 at toc@l(3)
+; PC64LE9-NEXT: xxmrghd 35, 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
+ <4 x float><float 42.0, float 43.0,
+ float 44.0, float 45.0>,
+ metadata !"fpexcept.strict") #1
+ ret <4 x double> %result
+}
+
+define <1 x float> @constrained_vector_ceil_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_ceil_v1f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI135_0 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI135_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI135_1 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI135_1 at toc@l(3)
+; PC64LE-NEXT: xsrdpip 0, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI135_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI135_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI135_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI135_1 at toc@l(3)
+; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
+ <1 x float> <float 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <1 x float> %ceil
+}
+
+define <2 x double> @constrained_vector_ceil_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_ceil_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI136_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI136_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI136_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: addi 3, 4, .LCPI136_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: xvrdpip 0, 0
+; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_ceil_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI136_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI136_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI136_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI136_1 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xvrdpip 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %ceil = call <2 x double> @llvm.experimental.constrained.ceil.v2f64(
+ <2 x double> <double 1.1, double 1.9>,
+ metadata !"fpexcept.strict") #1
+ ret <2 x double> %ceil
+}
+
+define <3 x float> @constrained_vector_ceil_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_ceil_v3f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI137_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI137_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI137_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI137_2 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI137_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI137_2 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI137_3 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI137_3 at toc@l
+; PC64LE-NEXT: xsrdpip 0, 0
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xsrdpip 0, 1
+; PC64LE-NEXT: xsrdpip 0, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_ceil_v3f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI137_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI137_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI137_1 at toc@ha
+; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI137_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI137_2 at toc@ha
+; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI137_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI137_3 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI137_3 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
+ <3 x float> <float 1.5, float 2.5, float 3.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x float> %ceil
+}
+
+define <3 x double> @constrained_vector_ceil_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_ceil_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI138_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI138_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI138_0 at toc@l(3)
+; PC64LE-NEXT: addi 3, 4, .LCPI138_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI138_2 at toc@ha
+; PC64LE-NEXT: xsrdpip 0, 0
+; PC64LE-NEXT: xvrdpip 0, 1
+; PC64LE-NEXT: lfs 1, .LCPI138_2 at toc@l(3)
+; PC64LE-NEXT: fmr 2, 1
+; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_ceil_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI138_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI138_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI138_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI138_1 at toc@l
+; PC64LE9-NEXT: xsrdpip 0, 0
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI138_2 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI138_2 at toc@l(3)
+; PC64LE9-NEXT: xvrdpip 0, 0
+; PC64LE9-NEXT: fmr 2, 1
+; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: blr
+entry:
+ %ceil = call <3 x double> @llvm.experimental.constrained.ceil.v3f64(
+ <3 x double> <double 1.1, double 1.9, double 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x double> %ceil
+}
+
+define <1 x float> @constrained_vector_floor_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_floor_v1f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI139_0 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI139_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI139_1 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI139_1 at toc@l(3)
+; PC64LE-NEXT: xsrdpim 0, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_floor_v1f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI139_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI139_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI139_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI139_1 at toc@l(3)
+; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
+ <1 x float> <float 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <1 x float> %floor
+}
+
+
+define <2 x double> @constrained_vector_floor_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_floor_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI140_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI140_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI140_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: addi 3, 4, .LCPI140_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: xvrdpim 0, 0
+; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_floor_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI140_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI140_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI140_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI140_1 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xvrdpim 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %floor = call <2 x double> @llvm.experimental.constrained.floor.v2f64(
+ <2 x double> <double 1.1, double 1.9>,
+ metadata !"fpexcept.strict") #1
+ ret <2 x double> %floor
+}
+
+define <3 x float> @constrained_vector_floor_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_floor_v3f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI141_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI141_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI141_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI141_2 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI141_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI141_2 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI141_3 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI141_3 at toc@l
+; PC64LE-NEXT: xsrdpim 0, 0
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xsrdpim 0, 1
+; PC64LE-NEXT: xsrdpim 0, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_floor_v3f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI141_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI141_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI141_1 at toc@ha
+; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI141_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI141_2 at toc@ha
+; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI141_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI141_3 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI141_3 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
+ <3 x float> <float 1.5, float 2.5, float 3.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x float> %floor
+}
+
+define <3 x double> @constrained_vector_floor_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_floor_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI142_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI142_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI142_0 at toc@l(3)
+; PC64LE-NEXT: addi 3, 4, .LCPI142_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI142_2 at toc@ha
+; PC64LE-NEXT: xsrdpim 0, 0
+; PC64LE-NEXT: xvrdpim 0, 1
+; PC64LE-NEXT: lfs 1, .LCPI142_2 at toc@l(3)
+; PC64LE-NEXT: fmr 2, 1
+; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_floor_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI142_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI142_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI142_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI142_1 at toc@l
+; PC64LE9-NEXT: xsrdpim 0, 0
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI142_2 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI142_2 at toc@l(3)
+; PC64LE9-NEXT: xvrdpim 0, 0
+; PC64LE9-NEXT: fmr 2, 1
+; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: blr
+entry:
+ %floor = call <3 x double> @llvm.experimental.constrained.floor.v3f64(
+ <3 x double> <double 1.1, double 1.9, double 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x double> %floor
+}
+
+define <1 x float> @constrained_vector_round_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_round_v1f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI143_0 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI143_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI143_1 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI143_1 at toc@l(3)
+; PC64LE-NEXT: xsrdpi 0, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_round_v1f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI143_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI143_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI143_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI143_1 at toc@l(3)
+; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
+ <1 x float> <float 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <1 x float> %round
+}
+
+define <2 x double> @constrained_vector_round_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_round_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI144_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI144_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI144_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: addi 3, 4, .LCPI144_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: xvrdpi 0, 0
+; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_round_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI144_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI144_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI144_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI144_1 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xvrdpi 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %round = call <2 x double> @llvm.experimental.constrained.round.v2f64(
+ <2 x double> <double 1.1, double 1.9>,
+ metadata !"fpexcept.strict") #1
+ ret <2 x double> %round
+}
+
+define <3 x float> @constrained_vector_round_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_round_v3f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI145_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI145_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI145_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI145_2 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI145_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI145_2 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI145_3 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI145_3 at toc@l
+; PC64LE-NEXT: xsrdpi 0, 0
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xsrdpi 0, 1
+; PC64LE-NEXT: xsrdpi 0, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_round_v3f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI145_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI145_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI145_1 at toc@ha
+; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI145_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI145_2 at toc@ha
+; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI145_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI145_3 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI145_3 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
+ <3 x float> <float 1.5, float 2.5, float 3.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x float> %round
+}
+
+
+define <3 x double> @constrained_vector_round_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_round_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 4, 2, .LCPI146_1 at toc@ha
+; PC64LE-NEXT: addis 3, 2, .LCPI146_0 at toc@ha
+; PC64LE-NEXT: addi 4, 4, .LCPI146_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 4
+; PC64LE-NEXT: addis 4, 2, .LCPI146_3 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI146_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI146_2 at toc@ha
+; PC64LE-NEXT: lfs 2, .LCPI146_3 at toc@l(4)
+; PC64LE-NEXT: xsrdpi 0, 0
+; PC64LE-NEXT: xvrdpi 0, 1
+; PC64LE-NEXT: lfs 1, .LCPI146_2 at toc@l(3)
+; PC64LE-NEXT: fmr 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_round_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI146_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI146_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI146_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI146_1 at toc@l
+; PC64LE9-NEXT: xsrdpi 0, 0
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI146_2 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI146_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI146_3 at toc@ha
+; PC64LE9-NEXT: lfs 2, .LCPI146_3 at toc@l(3)
+; PC64LE9-NEXT: xvrdpi 0, 0
+; PC64LE9-NEXT: fmr 3, 2
+; PC64LE9-NEXT: blr
+entry:
+ %round = call <3 x double> @llvm.experimental.constrained.round.v3f64(
+ <3 x double> <double 1.1, double 1.9, double 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x double> %round
+}
+
+define <1 x float> @constrained_vector_trunc_v1f32() #0 {
+; PC64LE-LABEL: constrained_vector_trunc_v1f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI147_0 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI147_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI147_1 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI147_1 at toc@l(3)
+; PC64LE-NEXT: xsrdpiz 0, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI147_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI147_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI147_1 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI147_1 at toc@l(3)
+; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(
+ <1 x float> <float 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <1 x float> %trunc
+}
+
+define <2 x double> @constrained_vector_trunc_v2f64() #0 {
+; PC64LE-LABEL: constrained_vector_trunc_v2f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI148_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI148_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI148_0 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: addi 3, 4, .LCPI148_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: xvrdpiz 0, 0
+; PC64LE-NEXT: xxswapd 34, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_trunc_v2f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI148_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI148_0 at toc@l
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI148_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI148_1 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xvrdpiz 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %trunc = call <2 x double> @llvm.experimental.constrained.trunc.v2f64(
+ <2 x double> <double 1.1, double 1.9>,
+ metadata !"fpexcept.strict") #1
+ ret <2 x double> %trunc
+}
+
+define <3 x float> @constrained_vector_trunc_v3f32() #0 {
+; PC64LE-LABEL: constrained_vector_trunc_v3f32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI149_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI149_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI149_0 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI149_2 at toc@ha
+; PC64LE-NEXT: lfs 1, .LCPI149_1 at toc@l(4)
+; PC64LE-NEXT: lfs 2, .LCPI149_2 at toc@l(3)
+; PC64LE-NEXT: addis 3, 2, .LCPI149_3 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI149_3 at toc@l
+; PC64LE-NEXT: xsrdpiz 0, 0
+; PC64LE-NEXT: lvx 2, 0, 3
+; PC64LE-NEXT: xsrdpiz 0, 1
+; PC64LE-NEXT: xsrdpiz 0, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_trunc_v3f32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI149_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI149_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI149_1 at toc@ha
+; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI149_1 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI149_2 at toc@ha
+; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: lfs 0, .LCPI149_2 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI149_3 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI149_3 at toc@l
+; PC64LE9-NEXT: lxvx 34, 0, 3
+; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: blr
+entry:
+ %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
+ <3 x float> <float 1.5, float 2.5, float 3.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x float> %trunc
+}
+
+define <3 x double> @constrained_vector_trunc_v3f64() #0 {
+; PC64LE-LABEL: constrained_vector_trunc_v3f64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI150_0 at toc@ha
+; PC64LE-NEXT: addis 4, 2, .LCPI150_1 at toc@ha
+; PC64LE-NEXT: lfs 0, .LCPI150_0 at toc@l(3)
+; PC64LE-NEXT: addi 3, 4, .LCPI150_1 at toc@l
+; PC64LE-NEXT: lxvd2x 1, 0, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI150_2 at toc@ha
+; PC64LE-NEXT: xsrdpiz 0, 0
+; PC64LE-NEXT: xvrdpiz 0, 1
+; PC64LE-NEXT: lfs 1, .LCPI150_2 at toc@l(3)
+; PC64LE-NEXT: fmr 2, 1
+; PC64LE-NEXT: fmr 3, 1
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_trunc_v3f64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI150_0 at toc@ha
+; PC64LE9-NEXT: lfs 0, .LCPI150_0 at toc@l(3)
+; PC64LE9-NEXT: addis 3, 2, .LCPI150_1 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI150_1 at toc@l
+; PC64LE9-NEXT: xsrdpiz 0, 0
+; PC64LE9-NEXT: lxvx 0, 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI150_2 at toc@ha
+; PC64LE9-NEXT: lfs 1, .LCPI150_2 at toc@l(3)
+; PC64LE9-NEXT: xvrdpiz 0, 0
+; PC64LE9-NEXT: fmr 2, 1
+; PC64LE9-NEXT: fmr 3, 1
+; PC64LE9-NEXT: blr
+entry:
+ %trunc = call <3 x double> @llvm.experimental.constrained.trunc.v3f64(
+ <3 x double> <double 1.1, double 1.9, double 1.5>,
+ metadata !"fpexcept.strict") #1
+ ret <3 x double> %trunc
+}
+
+define <1 x double> @constrained_vector_sitofp_v1f64_v1i32(<1 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v1f64_v1i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprwa 0, 3
+; PC64LE-NEXT: xscvsxddp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v1f64_v1i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: xscvsxddp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x double>
+ @llvm.experimental.constrained.sitofp.v1f64.v1i32(<1 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x double> %result
+}
+
+define <1 x float> @constrained_vector_sitofp_v1f32_v1i32(<1 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v1f32_v1i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprwa 0, 3
+; PC64LE-NEXT: xscvsxdsp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v1f32_v1i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: xscvsxdsp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x float>
+ @llvm.experimental.constrained.sitofp.v1f32.v1i32(<1 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x float> %result
+}
+
+define <1 x double> @constrained_vector_sitofp_v1f64_v1i64(<1 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v1f64_v1i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: xscvsxddp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v1f64_v1i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvsxddp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x double>
+ @llvm.experimental.constrained.sitofp.v1f64.v1i64(<1 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x double> %result
+}
+
+define <1 x float> @constrained_vector_sitofp_v1f32_v1i64(<1 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v1f32_v1i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: xscvsxdsp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v1f32_v1i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvsxdsp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x float>
+ @llvm.experimental.constrained.sitofp.v1f32.v1i64(<1 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x float> %result
+}
+
+define <2 x double> @constrained_vector_sitofp_v2f64_v2i16(<2 x i16> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i16:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI155_0 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI155_0 at toc@l
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: addis 3, 2, .LCPI155_1 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI155_1 at toc@l
+; PC64LE-NEXT: lxvd2x 0, 0, 3
+; PC64LE-NEXT: vperm 2, 2, 2, 3
+; PC64LE-NEXT: xxswapd 35, 0
+; PC64LE-NEXT: vsld 2, 2, 3
+; PC64LE-NEXT: vsrad 2, 2, 3
+; PC64LE-NEXT: xvcvsxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI155_0 at toc@ha
+; PC64LE9-NEXT: addi 3, 3, .LCPI155_0 at toc@l
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: vperm 2, 2, 2, 3
+; PC64LE9-NEXT: vextsh2d 2, 2
+; PC64LE9-NEXT: xvcvsxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x double> @constrained_vector_sitofp_v2f64_v2i32(<2 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwa 0, 3
+; PC64LE-NEXT: mtfprwa 1, 4
+; PC64LE-NEXT: xscvsxddp 0, 0
+; PC64LE-NEXT: xscvsxddp 1, 1
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvsxddp 0, 0
+; PC64LE9-NEXT: mtfprwa 1, 3
+; PC64LE9-NEXT: xscvsxddp 1, 1
+; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x float> @constrained_vector_sitofp_v2f32_v2i32(<2 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v2f32_v2i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwa 0, 3
+; PC64LE-NEXT: mtfprwa 1, 4
+; PC64LE-NEXT: xscvsxdsp 0, 0
+; PC64LE-NEXT: xscvsxdsp 1, 1
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v2f32_v2i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x float>
+ @llvm.experimental.constrained.sitofp.v2f32.v2i32(<2 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x float> %result
+}
+
+define <2 x double> @constrained_vector_sitofp_v2f64_v2i64(<2 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v2f64_v2i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvsxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvsxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x float> @constrained_vector_sitofp_v2f32_v2i64(<2 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v2f32_v2i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrd 3, 34
+; PC64LE-NEXT: mffprd 4, 0
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: xscvsxdsp 0, 0
+; PC64LE-NEXT: xscvsxdsp 1, 1
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v2f32_v2i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mfvsrld 3, 34
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrd 3, 34
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x float>
+ @llvm.experimental.constrained.sitofp.v2f32.v2i64(<2 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x float> %result
+}
+
+define <3 x double> @constrained_vector_sitofp_v3f64_v3i32(<3 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v3f64_v3i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mfvsrwz 3, 34
+; PC64LE-NEXT: mtfprwa 3, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwa 0, 3
+; PC64LE-NEXT: mtfprwa 2, 4
+; PC64LE-NEXT: xscvsxddp 1, 0
+; PC64LE-NEXT: xscvsxddp 2, 2
+; PC64LE-NEXT: xscvsxddp 3, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v3f64_v3i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvsxddp 1, 0
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: xscvsxddp 2, 0
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: xscvsxddp 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x double>
+ @llvm.experimental.constrained.sitofp.v3f64.v3i32(<3 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x double> %result
+}
+
+define <3 x float> @constrained_vector_sitofp_v3f32_v3i32(<3 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: addis 3, 2, .LCPI161_0 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI161_0 at toc@l
+; PC64LE-NEXT: mffprwz 4, 0
+; PC64LE-NEXT: mffprwz 5, 1
+; PC64LE-NEXT: mtfprwa 0, 4
+; PC64LE-NEXT: mtfprwa 1, 5
+; PC64LE-NEXT: xscvsxdsp 0, 0
+; PC64LE-NEXT: xscvsxdsp 1, 1
+; PC64LE-NEXT: mfvsrwz 4, 34
+; PC64LE-NEXT: mtfprwa 2, 4
+; PC64LE-NEXT: xscvsxdsp 2, 2
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xscvdpspn 0, 2
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI161_0 at toc@ha
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: addi 3, 3, .LCPI161_0 at toc@l
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 3, 4, 3
+; PC64LE9-NEXT: lxvx 36, 0, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vperm 2, 2, 3, 4
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x float>
+ @llvm.experimental.constrained.sitofp.v3f32.v3i32(<3 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x float> %result
+}
+
+define <3 x double> @constrained_vector_sitofp_v3f64_v3i64(<3 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v3f64_v3i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 2, 4
+; PC64LE-NEXT: mtfprd 3, 5
+; PC64LE-NEXT: xscvsxddp 1, 0
+; PC64LE-NEXT: xscvsxddp 2, 2
+; PC64LE-NEXT: xscvsxddp 3, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v3f64_v3i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvsxddp 1, 0
+; PC64LE9-NEXT: mtfprd 0, 4
+; PC64LE9-NEXT: xscvsxddp 2, 0
+; PC64LE9-NEXT: mtfprd 0, 5
+; PC64LE9-NEXT: xscvsxddp 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x double>
+ @llvm.experimental.constrained.sitofp.v3f64.v3i64(<3 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x double> %result
+}
+
+define <3 x float> @constrained_vector_sitofp_v3f32_v3i64(<3 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v3f32_v3i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: addis 6, 2, .LCPI163_0 at toc@ha
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: addi 3, 6, .LCPI163_0 at toc@l
+; PC64LE-NEXT: xscvsxdsp 0, 0
+; PC64LE-NEXT: xscvsxdsp 1, 1
+; PC64LE-NEXT: mtfprd 2, 5
+; PC64LE-NEXT: xscvsxdsp 2, 2
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xscvdpspn 0, 2
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI163_0 at toc@ha
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: addi 3, 3, .LCPI163_0 at toc@l
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 4
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 5
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x float>
+ @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x float> %result
+}
+
+define <4 x double> @constrained_vector_sitofp_v4f64_v4i32(<4 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v4f64_v4i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrwz 3, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mtfprwa 2, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwa 1, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mtfprwa 3, 4
+; PC64LE-NEXT: xscvsxddp 0, 2
+; PC64LE-NEXT: mtfprwa 2, 3
+; PC64LE-NEXT: xscvsxddp 1, 1
+; PC64LE-NEXT: xscvsxddp 3, 3
+; PC64LE-NEXT: xscvsxddp 2, 2
+; PC64LE-NEXT: xxmrghd 34, 3, 1
+; PC64LE-NEXT: xxmrghd 35, 2, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v4f64_v4i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwa 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvsxddp 0, 0
+; PC64LE9-NEXT: mtfprwa 1, 3
+; PC64LE9-NEXT: li 3, 12
+; PC64LE9-NEXT: xscvsxddp 1, 1
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: mtfprwa 1, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: mtfprwa 2, 3
+; PC64LE9-NEXT: xscvsxddp 1, 1
+; PC64LE9-NEXT: xscvsxddp 2, 2
+; PC64LE9-NEXT: xxlor 34, 0, 0
+; PC64LE9-NEXT: xxmrghd 35, 1, 2
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x double>
+ @llvm.experimental.constrained.sitofp.v4f64.v4i32(<4 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x double> %result
+}
+
+define <4 x float> @constrained_vector_sitofp_v4f32_v4i16(<4 x i16> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i16:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: vmrglh 2, 2, 2
+; PC64LE-NEXT: vspltisw 3, 8
+; PC64LE-NEXT: vadduwm 3, 3, 3
+; PC64LE-NEXT: vslw 2, 2, 3
+; PC64LE-NEXT: vsraw 2, 2, 3
+; PC64LE-NEXT: xvcvsxwsp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i16:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: vmrglh 2, 2, 2
+; PC64LE9-NEXT: vextsh2w 2, 2
+; PC64LE9-NEXT: xvcvsxwsp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.sitofp.v4f32.v4i16(<4 x i16> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
+}
+
+define <4 x float> @constrained_vector_sitofp_v4f32_v4i32(<4 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvsxwsp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvsxwsp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
+}
+
+define <4 x double> @constrained_vector_sitofp_v4f64_v4i64(<4 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v4f64_v4i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvsxddp 35, 35
+; PC64LE-NEXT: xvcvsxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v4f64_v4i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvsxddp 35, 35
+; PC64LE9-NEXT: xvcvsxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x double>
+ @llvm.experimental.constrained.sitofp.v4f64.v4i64(<4 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x double> %result
+}
+
+define <4 x float> @constrained_vector_sitofp_v4f32_v4i64(<4 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_sitofp_v4f32_v4i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrd 3, 34
+; PC64LE-NEXT: xxswapd 2, 35
+; PC64LE-NEXT: mfvsrd 4, 35
+; PC64LE-NEXT: mtfprd 1, 3
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mtfprd 0, 4
+; PC64LE-NEXT: mtfprd 3, 3
+; PC64LE-NEXT: mffprd 3, 2
+; PC64LE-NEXT: xscvsxdsp 1, 1
+; PC64LE-NEXT: mtfprd 2, 3
+; PC64LE-NEXT: xscvsxdsp 0, 0
+; PC64LE-NEXT: xscvsxdsp 3, 3
+; PC64LE-NEXT: xscvsxdsp 2, 2
+; PC64LE-NEXT: xxmrghd 0, 0, 1
+; PC64LE-NEXT: xxmrghd 1, 2, 3
+; PC64LE-NEXT: xvcvdpsp 34, 0
+; PC64LE-NEXT: xvcvdpsp 35, 1
+; PC64LE-NEXT: vmrgew 2, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_sitofp_v4f32_v4i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mfvsrld 3, 34
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrld 3, 35
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: mtfprd 1, 3
+; PC64LE9-NEXT: mfvsrd 3, 34
+; PC64LE9-NEXT: xscvsxdsp 1, 1
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 36, 0
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrd 3, 35
+; PC64LE9-NEXT: mtfprd 1, 3
+; PC64LE9-NEXT: xscvsxdsp 0, 0
+; PC64LE9-NEXT: xscvsxdsp 1, 1
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 34, 0
+; PC64LE9-NEXT: vmrgew 2, 2, 4
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.sitofp.v4f32.v4i64(<4 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
+}
+
+define <1 x double> @constrained_vector_uitofp_v1f64_v1i32(<1 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v1f64_v1i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprwz 0, 3
+; PC64LE-NEXT: xscvuxddp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v1f64_v1i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: xscvuxddp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x double>
+ @llvm.experimental.constrained.uitofp.v1f64.v1i32(<1 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x double> %result
+}
+
+define <1 x float> @constrained_vector_uitofp_v1f32_v1i32(<1 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v1f32_v1i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprwz 0, 3
+; PC64LE-NEXT: xscvuxdsp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v1f32_v1i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: xscvuxdsp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x float>
+ @llvm.experimental.constrained.uitofp.v1f32.v1i32(<1 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x float> %result
+}
+
+define <1 x double> @constrained_vector_uitofp_v1f64_v1i64(<1 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v1f64_v1i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: xscvuxddp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v1f64_v1i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvuxddp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x double>
+ @llvm.experimental.constrained.uitofp.v1f64.v1i64(<1 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x double> %result
+}
+
+define <1 x float> @constrained_vector_uitofp_v1f32_v1i64(<1 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v1f32_v1i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: xscvuxdsp 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v1f32_v1i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvuxdsp 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <1 x float>
+ @llvm.experimental.constrained.uitofp.v1f32.v1i64(<1 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <1 x float> %result
+}
+
+define <2 x double> @constrained_vector_uitofp_v2f64_v2i16(<2 x i16> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i16:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: addis 3, 2, .LCPI173_0 at toc@ha
+; PC64LE-NEXT: xxlxor 36, 36, 36
+; PC64LE-NEXT: addi 3, 3, .LCPI173_0 at toc@l
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: xvcvuxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: addis 3, 2, .LCPI173_0 at toc@ha
+; PC64LE9-NEXT: xxlxor 36, 36, 36
+; PC64LE9-NEXT: addi 3, 3, .LCPI173_0 at toc@l
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
+; PC64LE9-NEXT: xvcvuxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x double> @constrained_vector_uitofp_v2f64_v2i32(<2 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwz 0, 3
+; PC64LE-NEXT: mtfprwz 1, 4
+; PC64LE-NEXT: xscvuxddp 0, 0
+; PC64LE-NEXT: xscvuxddp 1, 1
+; PC64LE-NEXT: xxmrghd 34, 1, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvuxddp 0, 0
+; PC64LE9-NEXT: mtfprwz 1, 3
+; PC64LE9-NEXT: xscvuxddp 1, 1
+; PC64LE9-NEXT: xxmrghd 34, 1, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.uitofp.v2f64.v2i32(<2 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x float> @constrained_vector_uitofp_v2f32_v2i32(<2 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v2f32_v2i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwz 0, 3
+; PC64LE-NEXT: mtfprwz 1, 4
+; PC64LE-NEXT: xscvuxdsp 0, 0
+; PC64LE-NEXT: xscvuxdsp 1, 1
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v2f32_v2i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x float>
+ @llvm.experimental.constrained.uitofp.v2f32.v2i32(<2 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x float> %result
+}
+
+define <2 x double> @constrained_vector_uitofp_v2f64_v2i64(<2 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v2f64_v2i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvuxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvuxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x double>
+ @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x double> %result
+}
+
+define <2 x float> @constrained_vector_uitofp_v2f32_v2i64(<2 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v2f32_v2i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrd 3, 34
+; PC64LE-NEXT: mffprd 4, 0
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: xscvuxdsp 0, 0
+; PC64LE-NEXT: xscvuxdsp 1, 1
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v2f32_v2i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mfvsrld 3, 34
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrd 3, 34
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 2, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <2 x float>
+ @llvm.experimental.constrained.uitofp.v2f32.v2i64(<2 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <2 x float> %result
+}
+
+define <3 x double> @constrained_vector_uitofp_v3f64_v3i32(<3 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v3f64_v3i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mfvsrwz 3, 34
+; PC64LE-NEXT: mtfprwz 3, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwz 0, 3
+; PC64LE-NEXT: mtfprwz 2, 4
+; PC64LE-NEXT: xscvuxddp 1, 0
+; PC64LE-NEXT: xscvuxddp 2, 2
+; PC64LE-NEXT: xscvuxddp 3, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v3f64_v3i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvuxddp 1, 0
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: xscvuxddp 2, 0
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: xscvuxddp 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x double>
+ @llvm.experimental.constrained.uitofp.v3f64.v3i32(<3 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x double> %result
+}
+
+define <3 x float> @constrained_vector_uitofp_v3f32_v3i32(<3 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: addis 3, 2, .LCPI179_0 at toc@ha
+; PC64LE-NEXT: addi 3, 3, .LCPI179_0 at toc@l
+; PC64LE-NEXT: mffprwz 4, 0
+; PC64LE-NEXT: mffprwz 5, 1
+; PC64LE-NEXT: mtfprwz 0, 4
+; PC64LE-NEXT: mtfprwz 1, 5
+; PC64LE-NEXT: xscvuxdsp 0, 0
+; PC64LE-NEXT: xscvuxdsp 1, 1
+; PC64LE-NEXT: mfvsrwz 4, 34
+; PC64LE-NEXT: mtfprwz 2, 4
+; PC64LE-NEXT: xscvuxdsp 2, 2
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xscvdpspn 0, 2
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI179_0 at toc@ha
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: addi 3, 3, .LCPI179_0 at toc@l
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: vmrghw 3, 4, 3
+; PC64LE9-NEXT: lxvx 36, 0, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: vperm 2, 2, 3, 4
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x float>
+ @llvm.experimental.constrained.uitofp.v3f32.v3i32(<3 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x float> %result
+}
+
+define <3 x double> @constrained_vector_uitofp_v3f64_v3i64(<3 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v3f64_v3i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: mtfprd 2, 4
+; PC64LE-NEXT: mtfprd 3, 5
+; PC64LE-NEXT: xscvuxddp 1, 0
+; PC64LE-NEXT: xscvuxddp 2, 2
+; PC64LE-NEXT: xscvuxddp 3, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v3f64_v3i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: xscvuxddp 1, 0
+; PC64LE9-NEXT: mtfprd 0, 4
+; PC64LE9-NEXT: xscvuxddp 2, 0
+; PC64LE9-NEXT: mtfprd 0, 5
+; PC64LE9-NEXT: xscvuxddp 3, 0
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x double>
+ @llvm.experimental.constrained.uitofp.v3f64.v3i64(<3 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x double> %result
+}
+
+define <3 x float> @constrained_vector_uitofp_v3f32_v3i64(<3 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v3f32_v3i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: mtfprd 0, 3
+; PC64LE-NEXT: addis 6, 2, .LCPI181_0 at toc@ha
+; PC64LE-NEXT: mtfprd 1, 4
+; PC64LE-NEXT: addi 3, 6, .LCPI181_0 at toc@l
+; PC64LE-NEXT: xscvuxdsp 0, 0
+; PC64LE-NEXT: xscvuxdsp 1, 1
+; PC64LE-NEXT: mtfprd 2, 5
+; PC64LE-NEXT: xscvuxdsp 2, 2
+; PC64LE-NEXT: xscvdpspn 0, 0
+; PC64LE-NEXT: xscvdpspn 1, 1
+; PC64LE-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE-NEXT: xscvdpspn 0, 2
+; PC64LE-NEXT: xxsldwi 35, 1, 1, 3
+; PC64LE-NEXT: vmrghw 2, 3, 2
+; PC64LE-NEXT: lvx 3, 0, 3
+; PC64LE-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE-NEXT: vperm 2, 4, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: addis 3, 2, .LCPI181_0 at toc@ha
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: addi 3, 3, .LCPI181_0 at toc@l
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 34, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 4
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 35, 0, 0, 3
+; PC64LE9-NEXT: mtfprd 0, 5
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: vmrghw 2, 3, 2
+; PC64LE9-NEXT: lxvx 35, 0, 3
+; PC64LE9-NEXT: xscvdpspn 0, 0
+; PC64LE9-NEXT: xxsldwi 36, 0, 0, 3
+; PC64LE9-NEXT: vperm 2, 4, 2, 3
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <3 x float>
+ @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <3 x float> %result
+}
+
+define <4 x double> @constrained_vector_uitofp_v4f64_v4i32(<4 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v4f64_v4i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrwz 3, 34
+; PC64LE-NEXT: xxsldwi 1, 34, 34, 1
+; PC64LE-NEXT: mtfprwz 2, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: xxsldwi 0, 34, 34, 3
+; PC64LE-NEXT: mffprwz 4, 1
+; PC64LE-NEXT: mtfprwz 1, 3
+; PC64LE-NEXT: mffprwz 3, 0
+; PC64LE-NEXT: mtfprwz 3, 4
+; PC64LE-NEXT: xscvuxddp 0, 2
+; PC64LE-NEXT: mtfprwz 2, 3
+; PC64LE-NEXT: xscvuxddp 1, 1
+; PC64LE-NEXT: xscvuxddp 3, 3
+; PC64LE-NEXT: xscvuxddp 2, 2
+; PC64LE-NEXT: xxmrghd 34, 3, 1
+; PC64LE-NEXT: xxmrghd 35, 2, 0
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v4f64_v4i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: li 3, 0
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: mtfprwz 0, 3
+; PC64LE9-NEXT: li 3, 4
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xscvuxddp 0, 0
+; PC64LE9-NEXT: mtfprwz 1, 3
+; PC64LE9-NEXT: li 3, 12
+; PC64LE9-NEXT: xscvuxddp 1, 1
+; PC64LE9-NEXT: vextuwrx 3, 3, 2
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: mtfprwz 1, 3
+; PC64LE9-NEXT: mfvsrwz 3, 34
+; PC64LE9-NEXT: mtfprwz 2, 3
+; PC64LE9-NEXT: xscvuxddp 1, 1
+; PC64LE9-NEXT: xscvuxddp 2, 2
+; PC64LE9-NEXT: xxlor 34, 0, 0
+; PC64LE9-NEXT: xxmrghd 35, 1, 2
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x double>
+ @llvm.experimental.constrained.uitofp.v4f64.v4i32(<4 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x double> %result
+}
+
+define <4 x float> @constrained_vector_uitofp_v4f32_v4i16(<4 x i16> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i16:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxlxor 35, 35, 35
+; PC64LE-NEXT: vmrglh 2, 3, 2
+; PC64LE-NEXT: xvcvuxwsp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i16:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xxlxor 35, 35, 35
+; PC64LE9-NEXT: vmrglh 2, 3, 2
+; PC64LE9-NEXT: xvcvuxwsp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.uitofp.v4f32.v4i16(<4 x i16> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
+}
+
+define <4 x float> @constrained_vector_uitofp_v4f32_v4i32(<4 x i32> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i32:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvuxwsp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i32:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvuxwsp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
+}
+
+define <4 x double> @constrained_vector_uitofp_v4f64_v4i64(<4 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v4f64_v4i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xvcvuxddp 35, 35
+; PC64LE-NEXT: xvcvuxddp 34, 34
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v4f64_v4i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: xvcvuxddp 35, 35
+; PC64LE9-NEXT: xvcvuxddp 34, 34
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x double>
+ @llvm.experimental.constrained.uitofp.v4f64.v4i64(<4 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x double> %result
+}
+
+define <4 x float> @constrained_vector_uitofp_v4f32_v4i64(<4 x i64> %x) #0 {
+; PC64LE-LABEL: constrained_vector_uitofp_v4f32_v4i64:
+; PC64LE: # %bb.0: # %entry
+; PC64LE-NEXT: xxswapd 0, 34
+; PC64LE-NEXT: mfvsrd 3, 34
+; PC64LE-NEXT: xxswapd 2, 35
+; PC64LE-NEXT: mfvsrd 4, 35
+; PC64LE-NEXT: mtfprd 1, 3
+; PC64LE-NEXT: mffprd 3, 0
+; PC64LE-NEXT: mtfprd 0, 4
+; PC64LE-NEXT: mtfprd 3, 3
+; PC64LE-NEXT: mffprd 3, 2
+; PC64LE-NEXT: xscvuxdsp 1, 1
+; PC64LE-NEXT: mtfprd 2, 3
+; PC64LE-NEXT: xscvuxdsp 0, 0
+; PC64LE-NEXT: xscvuxdsp 3, 3
+; PC64LE-NEXT: xscvuxdsp 2, 2
+; PC64LE-NEXT: xxmrghd 0, 0, 1
+; PC64LE-NEXT: xxmrghd 1, 2, 3
+; PC64LE-NEXT: xvcvdpsp 34, 0
+; PC64LE-NEXT: xvcvdpsp 35, 1
+; PC64LE-NEXT: vmrgew 2, 2, 3
+; PC64LE-NEXT: blr
+;
+; PC64LE9-LABEL: constrained_vector_uitofp_v4f32_v4i64:
+; PC64LE9: # %bb.0: # %entry
+; PC64LE9-NEXT: mfvsrld 3, 34
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrld 3, 35
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: mtfprd 1, 3
+; PC64LE9-NEXT: mfvsrd 3, 34
+; PC64LE9-NEXT: xscvuxdsp 1, 1
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 36, 0
+; PC64LE9-NEXT: mtfprd 0, 3
+; PC64LE9-NEXT: mfvsrd 3, 35
+; PC64LE9-NEXT: mtfprd 1, 3
+; PC64LE9-NEXT: xscvuxdsp 0, 0
+; PC64LE9-NEXT: xscvuxdsp 1, 1
+; PC64LE9-NEXT: xxmrghd 0, 1, 0
+; PC64LE9-NEXT: xvcvdpsp 34, 0
+; PC64LE9-NEXT: vmrgew 2, 2, 4
+; PC64LE9-NEXT: blr
+entry:
+ %result = call <4 x float>
+ @llvm.experimental.constrained.uitofp.v4f32.v4i64(<4 x i64> %x,
+ metadata !"round.dynamic",
+ metadata !"fpexcept.strict") #0
+ ret <4 x float> %result
}
attributes #0 = { nounwind strictfp noimplicitfloat }
@@ -6472,12 +8815,30 @@ declare <2 x double> @llvm.experimental.constrained.rint.v2f64(<2 x double>, met
declare <2 x double> @llvm.experimental.constrained.nearbyint.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.maxnum.v2f64(<2 x double>, <2 x double>, metadata)
declare <2 x double> @llvm.experimental.constrained.minnum.v2f64(<2 x double>, <2 x double>, metadata)
+declare <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f32(<2 x float>, metadata)
+declare <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(<2 x float>, metadata)
+declare <2 x i32> @llvm.experimental.constrained.fptosi.v2i32.v2f64(<2 x double>, metadata)
+declare <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(<2 x double>, metadata)
+declare <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f32(<2 x float>, metadata)
+declare <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f32(<2 x float>, metadata)
+declare <2 x i32> @llvm.experimental.constrained.fptoui.v2i32.v2f64(<2 x double>, metadata)
+declare <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double>, metadata)
declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata)
declare <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(<2 x float>, metadata)
declare <2 x double> @llvm.experimental.constrained.ceil.v2f64(<2 x double>, metadata)
declare <2 x double> @llvm.experimental.constrained.floor.v2f64(<2 x double>, metadata)
declare <2 x double> @llvm.experimental.constrained.round.v2f64(<2 x double>, metadata)
declare <2 x double> @llvm.experimental.constrained.trunc.v2f64(<2 x double>, metadata)
+declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i32(<2 x i32>, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i32(<2 x i32>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64>, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.sitofp.v2f32.v2i64(<2 x i64>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i32(<2 x i32>, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i32(<2 x i32>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64>, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.uitofp.v2f32.v2i64(<2 x i64>, metadata, metadata)
; Scalar width declarations
declare <1 x float> @llvm.experimental.constrained.fadd.v1f32(<1 x float>, <1 x float>, metadata, metadata)
@@ -6499,12 +8860,28 @@ declare <1 x float> @llvm.experimental.constrained.rint.v1f32(<1 x float>, metad
declare <1 x float> @llvm.experimental.constrained.nearbyint.v1f32(<1 x float>, metadata, metadata)
declare <1 x float> @llvm.experimental.constrained.maxnum.v1f32(<1 x float>, <1 x float>, metadata)
declare <1 x float> @llvm.experimental.constrained.minnum.v1f32(<1 x float>, <1 x float>, metadata)
+declare <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f32(<1 x float>, metadata)
+declare <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f32(<1 x float>, metadata)
+declare <1 x i32> @llvm.experimental.constrained.fptosi.v1i32.v1f64(<1 x double>, metadata)
+declare <1 x i64> @llvm.experimental.constrained.fptosi.v1i64.v1f64(<1 x double>, metadata)
+declare <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f32(<1 x float>, metadata)
+declare <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f32(<1 x float>, metadata)
+declare <1 x i32> @llvm.experimental.constrained.fptoui.v1i32.v1f64(<1 x double>, metadata)
+declare <1 x i64> @llvm.experimental.constrained.fptoui.v1i64.v1f64(<1 x double>, metadata)
declare <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(<1 x double>, metadata, metadata)
declare <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(<1 x float>, metadata)
declare <1 x float> @llvm.experimental.constrained.ceil.v1f32(<1 x float>, metadata)
declare <1 x float> @llvm.experimental.constrained.floor.v1f32(<1 x float>, metadata)
declare <1 x float> @llvm.experimental.constrained.round.v1f32(<1 x float>, metadata)
declare <1 x float> @llvm.experimental.constrained.trunc.v1f32(<1 x float>, metadata)
+declare <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i32(<1 x i32>, metadata, metadata)
+declare <1 x float> @llvm.experimental.constrained.sitofp.v1f32.v1i32(<1 x i32>, metadata, metadata)
+declare <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i64(<1 x i64>, metadata, metadata)
+declare <1 x float> @llvm.experimental.constrained.sitofp.v1f32.v1i64(<1 x i64>, metadata, metadata)
+declare <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i32(<1 x i32>, metadata, metadata)
+declare <1 x float> @llvm.experimental.constrained.uitofp.v1f32.v1i32(<1 x i32>, metadata, metadata)
+declare <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i64(<1 x i64>, metadata, metadata)
+declare <1 x float> @llvm.experimental.constrained.uitofp.v1f32.v1i64(<1 x i64>, metadata, metadata)
; Illegal width declarations
declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata)
@@ -6545,6 +8922,14 @@ declare <3 x float> @llvm.experimental.constrained.maxnum.v3f32(<3 x float>, <3
declare <3 x double> @llvm.experimental.constrained.maxnum.v3f64(<3 x double>, <3 x double>, metadata)
declare <3 x float> @llvm.experimental.constrained.minnum.v3f32(<3 x float>, <3 x float>, metadata)
declare <3 x double> @llvm.experimental.constrained.minnum.v3f64(<3 x double>, <3 x double>, metadata)
+declare <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32(<3 x float>, metadata)
+declare <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f32(<3 x float>, metadata)
+declare <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(<3 x double>, metadata)
+declare <3 x i64> @llvm.experimental.constrained.fptosi.v3i64.v3f64(<3 x double>, metadata)
+declare <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32(<3 x float>, metadata)
+declare <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f32(<3 x float>, metadata)
+declare <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(<3 x double>, metadata)
+declare <3 x i64> @llvm.experimental.constrained.fptoui.v3i64.v3f64(<3 x double>, metadata)
declare <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(<3 x double>, metadata, metadata)
declare <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(<3 x float>, metadata)
declare <3 x float> @llvm.experimental.constrained.ceil.v3f32(<3 x float>, metadata)
@@ -6555,6 +8940,14 @@ declare <3 x float> @llvm.experimental.constrained.round.v3f32(<3 x float>, meta
declare <3 x double> @llvm.experimental.constrained.round.v3f64(<3 x double>, metadata)
declare <3 x float> @llvm.experimental.constrained.trunc.v3f32(<3 x float>, metadata)
declare <3 x double> @llvm.experimental.constrained.trunc.v3f64(<3 x double>, metadata)
+declare <3 x double> @llvm.experimental.constrained.sitofp.v3f64.v3i32(<3 x i32>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.sitofp.v3f32.v3i32(<3 x i32>, metadata, metadata)
+declare <3 x double> @llvm.experimental.constrained.sitofp.v3f64.v3i64(<3 x i64>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64>, metadata, metadata)
+declare <3 x double> @llvm.experimental.constrained.uitofp.v3f64.v3i32(<3 x i32>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.uitofp.v3f32.v3i32(<3 x i32>, metadata, metadata)
+declare <3 x double> @llvm.experimental.constrained.uitofp.v3f64.v3i64(<3 x i64>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64>, metadata, metadata)
; Double width declarations
declare <4 x double> @llvm.experimental.constrained.fadd.v4f64(<4 x double>, <4 x double>, metadata, metadata)
@@ -6576,9 +8969,27 @@ declare <4 x double> @llvm.experimental.constrained.rint.v4f64(<4 x double>, met
declare <4 x double> @llvm.experimental.constrained.nearbyint.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.maxnum.v4f64(<4 x double>, <4 x double>, metadata)
declare <4 x double> @llvm.experimental.constrained.minnum.v4f64(<4 x double>, <4 x double>, metadata)
+declare <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f32(<4 x float>, metadata)
+declare <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f32(<4 x float>, metadata)
+declare <4 x i32> @llvm.experimental.constrained.fptosi.v4i32.v4f64(<4 x double>, metadata)
+declare <4 x i64> @llvm.experimental.constrained.fptosi.v4i64.v4f64(<4 x double>, metadata)
+declare <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f32(<4 x float>, metadata)
+declare <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f32(<4 x float>, metadata)
+declare <4 x i32> @llvm.experimental.constrained.fptoui.v4i32.v4f64(<4 x double>, metadata)
+declare <4 x i64> @llvm.experimental.constrained.fptoui.v4i64.v4f64(<4 x double>, metadata)
declare <4 x float> @llvm.experimental.constrained.fptrunc.v4f32.v4f64(<4 x double>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(<4 x float>, metadata)
declare <4 x double> @llvm.experimental.constrained.ceil.v4f64(<4 x double>, metadata)
declare <4 x double> @llvm.experimental.constrained.floor.v4f64(<4 x double>, metadata)
declare <4 x double> @llvm.experimental.constrained.round.v4f64(<4 x double>, metadata)
declare <4 x double> @llvm.experimental.constrained.trunc.v4f64(<4 x double>, metadata)
+declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i16(<4 x i16>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.sitofp.v4f64.v4i32(<4 x i32>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.sitofp.v4f64.v4i64(<4 x i64>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i64(<4 x i64>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i16(<4 x i16>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.uitofp.v4f64.v4i32(<4 x i32>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.uitofp.v4f64.v4i64(<4 x i64>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i64(<4 x i64>, metadata, metadata)
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