[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally closed this revision.
cameron.mcinally added a comment.

Ah, you're right. I misread the register classes.

` def : SVE_InReg_Extend<nxv8i16, op, nxv8i1, nxv8i8, !cast<Instruction>(NAME # _H)>;`

I was reading `nxv16i8` instead of `nxv8i8` for the input operand. Since it's `nxv8i8`, they are unpacked.

I'll have to find a way to generate the nxv8i8 type, to cast the operand to it. Will take that to another Diff though...


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