[compiler-rt] df9a9bb - [X86] Correct the implementation of the testFeature macro in getIntelProcessorTypeAndSubtype to do a proper bit test.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-08-20T23:50:45-07:00
New Revision: df9a9bb7beb7bc04ca4188fe0e527baac2900ff1

URL: https://github.com/llvm/llvm-project/commit/df9a9bb7beb7bc04ca4188fe0e527baac2900ff1
DIFF: https://github.com/llvm/llvm-project/commit/df9a9bb7beb7bc04ca4188fe0e527baac2900ff1.diff

LOG: [X86] Correct the implementation of the testFeature macro in getIntelProcessorTypeAndSubtype to do a proper bit test.

Instead of ANDing with a one hot mask representing the bit to
be tested, we were ANDing with just the bit number. This tests
multiple bits none of them the correct one.

This caused skylake-avx512, cascadelake and cooperlake to all
be misdetected. Based on experiments with the Intel SDE, it seems
that all of these CPUs are being detected as being cooperlake.
This is bad since its the newest CPU of the 3.

Added: 
    

Modified: 
    compiler-rt/lib/builtins/cpu_model.c

Removed: 
    


################################################################################
diff  --git a/compiler-rt/lib/builtins/cpu_model.c b/compiler-rt/lib/builtins/cpu_model.c
index 8346bb62dcfb..468bcc84cbcb 100644
--- a/compiler-rt/lib/builtins/cpu_model.c
+++ b/compiler-rt/lib/builtins/cpu_model.c
@@ -277,7 +277,7 @@ getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
                                 const unsigned *Features,
                                 unsigned *Type, unsigned *Subtype) {
 #define testFeature(F)                                                         \
-  (Features[F / 32] & (F % 32)) != 0
+  (Features[F / 32] & (1 << (F % 32))) != 0
 
   // We select CPU strings to match the code in Host.cpp, but we don't use them
   // in compiler-rt.