[PATCH] D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops

Gabriel Hjort Ã…kerlund via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 19 03:19:27 PDT 2020


ehjogab created this revision.
ehjogab added reviewers: dsanders, arsenm, qcolombet, ab.
Herald added subscribers: bjope, rovka.
Herald added a project: LLVM.
ehjogab requested review of this revision.
Herald added a subscriber: wdng.

GlobalISelEmitter.cpp requires that destination pattern have the
register class annotated to its operands, e.g.:

  def : Pat<(add i32:$src1, i32:$str2),
            (instr regclass:$src1, regclass:$src2)>;

This information is not necessary for SelectionIDAG, and subsequently
for certain targets the register class is omitted from the operands,
which causes the pattern to be rejected. However, this information is
still available by looking at the corresponding operand in the
instruction definition. This patch performs such a lookup when a
register class is expected and none has been annotated to the operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86203

Files:
  llvm/test/TableGen/GlobalISelEmitter-unannotated-dst-pattern-ops.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp


Index: llvm/utils/TableGen/GlobalISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -3457,7 +3457,8 @@
   Expected<action_iterator>
   importExplicitUseRenderer(action_iterator InsertPt, RuleMatcher &Rule,
                             BuildMIAction &DstMIBuilder,
-                            TreePatternNode *DstChild);
+                            TreePatternNode *DstChild,
+                            Record *InstrOpNodeRec);
   Error importDefaultOperandRenderers(action_iterator InsertPt, RuleMatcher &M,
                                       BuildMIAction &DstMIBuilder,
                                       DagInit *DefaultOps) const;
@@ -4157,7 +4158,7 @@
 
 Expected<action_iterator> GlobalISelEmitter::importExplicitUseRenderer(
     action_iterator InsertPt, RuleMatcher &Rule, BuildMIAction &DstMIBuilder,
-    TreePatternNode *DstChild) {
+    TreePatternNode *DstChild, Record *InstrOpNodeRec) {
 
   const auto &SubOperand = Rule.getComplexSubOperand(DstChild->getName());
   if (SubOperand.hasValue()) {
@@ -4245,9 +4246,15 @@
   }
 
   // Otherwise, we're looking for a bog-standard RegisterClass operand.
-  if (auto *ChildDefInit = dyn_cast<DefInit>(DstChild->getLeafValue())) {
-    auto *ChildRec = ChildDefInit->getDef();
-
+  Record *ChildRec = nullptr;
+  if (auto *ChildDefInit = dyn_cast<DefInit>(DstChild->getLeafValue()))
+    ChildRec = ChildDefInit->getDef();
+  else if (dyn_cast<UnsetInit>(DstChild->getLeafValue()))
+    // If operand has uninitialized leaf value (meaning the operand has not been
+    // prefixed with anything), try using the register class from the 'ins'
+    // field.
+    ChildRec = InstrOpNodeRec;
+  if (ChildRec) {
     ArrayRef<TypeSetByHwMode> ChildTypes = DstChild->getExtTypes();
     if (ChildTypes.size() != 1)
       return failedImport("Dst pattern child has multiple results");
@@ -4592,7 +4599,8 @@
         CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
 
         auto InsertPtOrError =
-            importExplicitUseRenderer(InsertPt, M, DstMIBuilder, ValChild);
+            importExplicitUseRenderer(InsertPt, M, DstMIBuilder, ValChild,
+                                      nullptr);
         if (auto Error = InsertPtOrError.takeError())
           return std::move(Error);
         InsertPt = InsertPtOrError.get();
@@ -4661,7 +4669,8 @@
     }
 
     auto InsertPtOrError = importExplicitUseRenderer(InsertPt, M, DstMIBuilder,
-                                                     Dst->getChild(Child));
+                                                     Dst->getChild(Child),
+                                                     OperandNode);
     if (auto Error = InsertPtOrError.takeError())
       return std::move(Error);
     InsertPt = InsertPtOrError.get();
Index: llvm/test/TableGen/GlobalISelEmitter-unannotated-dst-pattern-ops.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/GlobalISelEmitter-unannotated-dst-pattern-ops.td
@@ -0,0 +1,30 @@
+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=true -I %p/../../include -I %p/Common -o - | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
+            [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
+
+// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 38, // Rule ID 0 //
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
+// CHECK-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)  =>  (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
+// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
+// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT: // GIR_Coverage, 0,
+// CHECK-NEXT: GIR_Done,
+// CHECK-NEXT: // Label 1: @38
+// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 47, // Rule ID 1 //
+// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (ADD:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2)
+// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
+// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT: // GIR_Coverage, 1,
+// CHECK-NEXT: GIR_Done,
+def : Pat<(add i32:$src1, i32:$src2),
+          (ADD $src1, $src2)>;


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