[PATCH] D86022: [ARM] Allow tail predication of VLDn

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

This has made me think a bit.. but it seems to make sense and from looking again at the existing checks, they look enough for correctness - to my pleasant surprise!
It feels odd though, that these instructions can't be used in a VPT block but we can use them here... I guess because they actually use mechanisms. But have we got confirmation that both/all registers are always guaranteed to be updated properly in a tail-predicated loop? I don't think there's anything in the reference manual about that limitation but I also haven't found it very clear anyway! One case which we'd have to avoid is if, in a horrible circumstance, LR is used as an address register which is post-indexed and predication could become UNKNOWN, but that isn't specific to VLD2/4.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86022/new/

https://reviews.llvm.org/D86022