[PATCH] D86063: AMDGPU: Match global saddr addressing mode

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kzhuravl.
Herald added subscribers: kerbowa, jfb, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, qcolombet.
Herald added a project: LLVM.
arsenm requested review of this revision.
Herald added a subscriber: wdng.

The previous implementation was incorrect, and based off incorrect
instruction definitions. Unfortunately we can't match natural
addressing in a lot of cases due to the shift/scale applied in
getelementptrs. This relies on reducing the 64-bit shift to 32-bits.


https://reviews.llvm.org/D86063

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/FLATInstructions.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/test/CodeGen/AMDGPU/clamp.ll
  llvm/test/CodeGen/AMDGPU/ds_read2.ll
  llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
  llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
  llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
  llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
  llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
  llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll
  llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll
  llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
  llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
  llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
  llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
  llvm/test/CodeGen/AMDGPU/madak.ll
  llvm/test/CodeGen/AMDGPU/max.i16.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/sdwa-op64-test.ll
  llvm/test/CodeGen/AMDGPU/sext-in-reg.ll
  llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
  llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
  llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/test/CodeGen/AMDGPU/v_cndmask.ll
  llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll