[PATCH] D85165: [X86][MC][Target] Initial backend support a tune CPU to support -mtune

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc7a0b2684f74: [X86][MC][Target] Initial backend support a tune CPU to support -mtune (authored by craig.topper).
Herald added a subscriber: jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D85165?vs=283036&id=285773#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85165/new/

https://reviews.llvm.org/D85165

Files:
  llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
  llvm/include/llvm/MC/MCSubtargetInfo.h
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/TargetSubtargetInfo.cpp
  llvm/lib/MC/MCSubtargetInfo.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
  llvm/lib/Target/ARM/ARMSubtarget.cpp
  llvm/lib/Target/ARM/ARMSubtarget.h
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/AVRSubtarget.cpp
  llvm/lib/Target/AVR/AVRSubtarget.h
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
  llvm/lib/Target/BPF/BPFSubtarget.cpp
  llvm/lib/Target/BPF/BPFSubtarget.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  llvm/lib/Target/Hexagon/HexagonSubtarget.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/LanaiSubtarget.cpp
  llvm/lib/Target/Lanai/LanaiSubtarget.h
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
  llvm/lib/Target/MSP430/MSP430Subtarget.cpp
  llvm/lib/Target/MSP430/MSP430Subtarget.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/Mips/MipsSubtarget.cpp
  llvm/lib/Target/Mips/MipsSubtarget.h
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
  llvm/lib/Target/NVPTX/NVPTXSubtarget.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.cpp
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/Sparc/SparcSubtarget.cpp
  llvm/lib/Target/Sparc/SparcSubtarget.h
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
  llvm/lib/Target/SystemZ/SystemZSubtarget.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
  llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86Subtarget.cpp
  llvm/lib/Target/X86/X86Subtarget.h
  llvm/lib/Target/X86/X86TargetMachine.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/lib/Target/XCore/XCoreSubtarget.cpp
  llvm/lib/Target/XCore/XCoreSubtarget.h
  llvm/unittests/CodeGen/MFCommon.inc
  llvm/utils/TableGen/SubtargetEmitter.cpp

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